a mARTIAN dIARY

Lately I have been seeing a lot of “organic” hits from Google onto my blog with keywords like “VLSI project” or “Main project VLSI”.  This reminded me back of the time 2 years back when I was at the other end of Google frantically searching for project ideas, heck, at least some info on how to make sense of a VLSI Project.  There has been a large explosion of different well paying VLSI related jobs  in India and hence the craze to do a VLSI project is understandable. I know of lot of people who already have a software job offer from multi domain companies and are hoping to do an impressive project to try and get into the VLSI department.

But the trouble is that, like with any electronic projects (not to belittle any software engineers as a software project also lends to similar difficulties) is that, conceiving the idea is one thing but getting it working in a satisfactory manner is a altogether different thing. And especially since VLSI domain is a comparatively new one, with hindsight, I believe that there are some things that need to be understood/ considered by the person before jumping into the world of VLSI. I am going to try to pen down these concepts/ considerations as a starting point for people trying to do the same.

Two Faces

Chip design is, in a very broad sense, two part affair. The first part of the design life cycle purely exists on a computer. At this sage you are designing your whole system, coding it, simulating it, and testing it etc in a computer using suitable software. This is true whether it Analog or Digital or FPGA or Custom ASIC. Once this stage reaches a decent enough level of maturity then the outputs from this state is “transferred” to Silicon. How and when this is done is dependent on what kind of a chip you are making.

Analog

When you talk about VLSI, it includes both analog and digital parts. I am a digital engineer and hence won’t be able to comment much on the Analog Projects. But still there are some concepts that are common which I shall explain. Like I said earlier, the first part of the design cycle is carried out entirely inside a computer. For analog and digital it would be different tools. I believe that analog uses tools like SPICE etc for doing transistor level simulation. Once this phase is over the output might be in for a mask file which will then need to be given to a foundry (in case of analog and custom ASIC) using which they will manufacture the chip and give it back to us.  I am not aware of any analog foundries that would take up work for academic projects.

Digital

Digital chips can be widely classified into Custom ASIC and Field Programmable

Custom ASIC

Its not proper terminology but for the purpose of this discussion I shall refer to all digital Chips that require to be manufactured at the foundry as Custom ASIC. If you know basic VLSI theory (Which I strongly suggest you learn if you are panning to do such a project ) you will understand that the manufacturing processes of ASIC’s involve a large number of “masks” that aid in the manufacture of the desired transistor -> gate structures. Depending on the number of masks that are programmed by the end user we can have different types of Chips which are a result of a trade-off. The more masks you can program, the more control you have over the logic and more efficient you chip but this is met with increasing costs too. In custom ASIC’s we have either no or only some of the mask’s being predefined, hence allowing greater programmability. For a more exhaustive discussion on this matter please refer John Smith’s excellent book or similar books.

Since these chips allow more programmability, they need to be designed at the transistor level or gate level using suitable software like MAGIC and then the masks that are the output need to be given to the foundries that would manufacture and give the chip back. Since you would be operating at the transistor level you can do only functionally very simple projects in this manner. Another option is that the foundries would give you their library cell definitions and you would have to write RTL (HDL) and “synthesize” netlists using these library components. You would then have to do layout and “close” the timing (remove volitions) and give that mask to the foundry. But this can be very hard to do due to non-availability of tools and also due to want of know-how

Semiconductor Complex, Chandigarh (Thanks to my friend Vaibhav Mathur )  is one such foundry in India. They also undertake academic projects between certain periods of time. This needs to be carefully considered while going in for a project. Also since you are starting at the transistor level and the level of abstraction is minimal, you need to take up seemingly simple projects, at least from the functional point of view.

Field Programmable

As their name suggests, they can be programmed from the comfort of ones home or college (some comfort eh?). You can possibly guess that we that lesser number of masks are programmable, i.e. the interconnect masks, the rest of the masks have special structures (ROM based or Look-Up Table based) that make this kind of programming possible. FPGA’s are one type of these chips with others including CPLD, PSoC, PLA, PAL etc

From a normal Indian college (that I came from) perspective this one of the most practical type of project to choose and also I did my main project on FPGA so I would be discussing more about it.

Continue reading part II

If you can get your job done with tr don’t use SED
If you can do it with SED don’t use AWK
If you can do it with AWK don’t use perl

One of the basic powers of UNIX based systems comes from the fact that there are a gazillion ways of doing even the simplest of tasks. With the combined philosophies of KISS and “Small is beautiful” implemented beautifully along with the pipelining and I/O redirection, the power can actually be overwhelming at times. This is exactly a stumbling point for a person new to this world, especially if he’s coming from the “click-click-click” philosophy of windows. Agreed, the latter philosophy is best suited for a general user who uses computer sparingly or for tasks such as browsing and chatting. The typical “Non-IT” portfolio.  But for an EDA engineer (like me) or a power user to think of a world without these tools is blasphemy. Still with so many choices available, a lot of people who would love to have the power dither away from the “right” path due to a sense of vastness.

I have held the view that languages are just means to end. Writing a program is not the hard part, its just the unavoidable detail.Any person with reasonable intelligence can use the IT industry mantra of {“CTRL+C-CTRL+V”} and write reasonable code. This is particularly true in the case scripting as the “hard” part such as memory management etc is removed. Hence we see that in the scripting mindset the focus is to get the job done and ask questions about efficiency etc later (unless it’s a heavily executed script and the current implantation is VERY bad). So the most important part of scripting boils down to the language/tool selection which can be a daunting task, taking the amount of choices available. Even though there can never be hard and fast rules , I thought I would pen down some thumb rules that can be applied to make this daunting task easy.

Never start with NO!
First thing to understand is that -: always be open to change…..but with intelligence. Don’t choose a language just because you’re comfortable with it. Even though there are exceptions to this rule like when time is playing a very important parameter in determining the value of the current solution or the complexity reduction offered to your with the new language does not justify the extra effort to be spent to get the thing implemented(Remember that the product of this first effort can be later used if the code is modularised) . I know this sounds vague but the idea I want to convey is that always consider other languages before committing to a particular language.A general flow for choosing a language is given at the end.

Visualize the Solution
Get a grip of the capabilities of the language rather than spend too much time learning the each and every syntax. More often than not, the time difference between when you learn the language and when you have to solve a practical problem would be too much that the intricacies that you spend hours learning would seen as distant to you as the basic syntax. Instead if you get the capabilities they it will help you visualize the solution in a particular language and the dirty stuff can be dealt with later. Chances are that most of the “challenges” that you have to face while implementation would have been faced by hundreds before and would be well documented so just GOOGLE!

Modularize it!
This is something I try to implement all the time. Once you visualize your solution, split it into independently implemental chunks. Not only does this help you write code that’s easily understandable/maintainable/modifiable but it also helps reduce your work when you are writing another script if you can reuse some of the modules.

Hybrids/ Genetic engineering is good.
Ever read about the plants that have insecticide genes engineered into them? Similarly , it might make sense to implement a part of the solution in one language and the other in another. As long as you can easily understand the way the data is to be transferred between the two parts, Go for it!

The following rules/questions can be used as a guideline while choosing the language.

It’s a simple solution involving a lot of individual UNIX commands / executables
Can I see the solution in Shell?

It involves rudimentary text processions, like single character substitution and some character removal
Can I see the solution with Shell along with cut and tr commands?

It involves more complex text manipulations
Can I see the solution in Shell and SED?
(AWK can do a log of things SED can do, but complex stream editing is something SED is better at (faster, the code is terser, etc.) but SED has no function and no arthemetic)

I also want some multilevel text manipulations and with support for variables during these complex text manipulation steps.
Can I see the solution in Shell and AWK?

It involves large scale text manipulation and reports parsing.
Can I visualize the solution in PERL? (or Python?)

It involves automation of interactive software like ftp, ssh etc
Can I see the solution with Expect along with a host language like TCL?

Please do leave a comment if you feel that there is anything else that you have come across that can make this more helpful. 

The following is what a nerd with a capital N writes in his diary about a particular shell scripting problem. To appreciate the situation, first understand the technicalities of the issue. When you invoke a piped “while” in bash, it creates a new sub-shell to run the program and thus what ever variables that you use inside the while, has only local scope. Hence when you get out, the modifications are lost. For a clearer picture of the actual technical issue please read

http://www.kilala.nl/Sysadmin/script-variablescope.php

(Please do not proceed without understanding the actual issue since I stand a chance of being grossly misinterpreted otherwise)

Dear Diary,

Today she (bash) behaved very badly with me. Like I have been telling you lately, She has been acting very strange. It’s like she’s a totally different person. Every day she comes up with more and more mood swings (modes via command switches) particularly while dealing with others that work with her (programs). Gone are the days when she knew what I wanted and I knew how to get it from her. The more I have gotten to know her, the lesser I have understood about her vagaries.I know I can’t interface with her as well as they (programs) do and I accept that but all I ask for  is  a little bit of consideration for my feelings. Is that too much to ask? But she’s not at all bothered of my feelings, telling that I am jealous and paranoid since it’s not her mood but her colleague’s (programs)   with whom she has to deal with (run). But I feel its cuz shes behaving so freely with them and giving them so much "permissions" (its a ubuntu system )

But today something happened, that really turned her argument on its head. I was playing around with her (for a) "while" and was pipeing some data into her "while" (construct). Everything was working fine while I was inside her, but the moment I got out, it was as though everything changed. She has no memory of me and all the things I had did inside her. Half an hour of work and no final effect and I actually thought she was enjoying it. I was very frustrated and did it again and again, but to the same tune.

After that I finally decided to ask around and would you believe it? Others know her better than Me . It seems her “while” is a separate person, like her inner child or something, and it transforms her into someone else (sub-process) and what ever I pipe into her is lost the moment I get out

Are all she(ll)s in this world two faced?

Good night

I was recently helping one of my juniors search for a seminar topic and I came across the idea of SDS (Software Defined Silicon). The following is some questions that where thrown at me while I was explaining it. A bagful of thanks to David Manners for his excellent article. Since the net is my primary source of information for me regarding this technology there might be mistakes in my understanding, so if you find any please leave a comment so that I can rectify it

Ok so what is it?
Software defined silicon is a new electronic device that is both low cost and easy to program.
 
At an abstract level, How is this different from existing ASIC/FPGA?
This is actually two questions. Traditionally Full/Partial custom ASIC is less costly that FPGA per unit when the volumes increase) where as FPGA is more suited for prototyping since the time taken for design changes to be translated to hardware is much lesser. So while choosing between FPGA and Custom ASIC is a trade-off between cost and programmability

SDS will offer the better programmability than FPGA at a much lesser cost than FPGA with lesser lead times and also in a single language (C)

At a abstract level, How is this different from existing micro processors?
Microprocessors are general purpose chips. They are designed with the traditional single threaded flow in mind. SDS can be called a "events-driven processor engine". An events-driven processor is one that is capable, when an event occurs, of executing software immediately, and then terminating, and waiting for the next event. The events are things like a pin changing state.
So it you would be able to write really "real-time" software whose performance can compare that to hardware. For example you can write real time communication protocol that’s traditionally implemented in hardware in software. Also in the creators own words “So we’ve taken a very responsive, fast, deterministic, real-time processor engine, and we’ve integrated into that very tight pin control”, says Hurley, “and we’ve developed a core-to-core communications interface. So now we can build arrays of cores that can control pins.”

Isn’t RTL similar to C?
At syntax level both are high level languages. But while writing RTL we need to be mindful of what hardware our code is going to infer so at the conceptual level its very different from C.

In one word?
“You’re implementing functionality that’s traditionally implemented in hardware in software”

How is the cost low even with better features?
From the silicon cost point of view, XMOS is using processors, which are silicon efficient, and RAM, which is the most silicon efficient structure. By using processors and RAM, it gains big cost advantages.

What about an example of development freedom?
“The development freedom the customer has is incredible because the customer can choose how to partition that capability”, says Hurley, “what’s really powerful is that a customer has a budget of processor cycles, he can choose how to spend that budget on real-time tasks such as interfaces, DSP, and control, and, more importantly, he is then able to dynamically alter that so, when they’re doing multiple products (typically consumer companies have a general platform supporting 20 or 30 products) he can choose to say: ‘I don’t want a UART in this design, but I do want to run an MP3 decoder. So I will remove the UART piece of code, and I will re-purpose those processing cycles into my DSP capability. I don’t believe anything in the market today can offer that level of capability to a customer.”

What does this mean for hardware engineers?
If this was to become the chip that survives the current war between FPGA /ASIC/PSoC/SDS , the hardware engineers outside this technology would starve

What does this mean for the software engineers?
They get more power as they can write more powerful code that can at a lot of level emulate hardware perfectly, Something that was not possible till now

What’s the different with respect to the design flow?
Usually the hardware flow would involve work on EDA software that would design the hardware to be implemented. The coding at this stage is usually done in RTL like verilog/ VHDL. Then if the hardware so implemented included processors software would be written run on the processor.
Here in SDS the design at the hardware level is generic. the resource you have is processor cycles that you can allot via your programming (in C with some additions for defining port structure and using multi-threading and parallelism) to the task to which you want to allot it to. So RTL coding is removed out of the flow.

"It’s a standard embedded software development flow starting with C/C++ source, compile, link, assemble and de-bug using standard industry development tools."

Ok what all can it currently do?
"SDS can run Ethernet MAC and the MII interface in software at 200Mbps, it has DSP capability and control capability"

So I am about to finish my first year as an EDA engineer. It does put me a scale up in terms of being an engineer with 1 year industry experience. Hurray(?)!!!.

Now how can I call it a COMPLETE year without attending one the Major calendar events in every EDA-using engineer’s year? Yep….this feeling was so strong that I finally registered for SNUG and Cadence Technology on tour and ended up attending them as well.  Here is what I thought of both

SNUG 2007

For the uninitiated,  SNUG stands for SyNopsys User Group and it is a yearly conference for users of synopsys tools (Synopsys being a major EDA tool vendor with Cadence Mentor Graphics and Magma being the other biggies). In hindsight, the turn-out was really good. Also, for me, working primarily on the synopsys tools, the organization of the tracks made sense. Tracks are basically parallel programs sessions specific to domain of the engineer. For synopsys its organized as “Physical Design & SignOff”, “Synthesis and Test”  and least but miles ahead of least (No I am not a verification engineer ) the “Verification and AMS” track. Since a lot of work in India takes palace in the verification field (so I am lead to believe), this track generally attracts the biggest crowds with “Synthesis and Test”  having the lowest participation.

We were asked to reach the place at around 7:15 ( Were they bonkers I wonder?) at Leela Palace and for a morning hater like me this was a pressure-point….but I managed to reach there by 8:30, pretty good considering it was still MORNING The registration was pretty hassle free as the kit and ID cards were already prepared for the pre-registered people and were set up in alphabetic order. We just needed to show our ID card to get the same. I knew that these EDA vendors are pretty generous with gifts but was really surprised to find a USB Mouse!!! and a Laptop Light!!! along with the kit. Not a total waste already eh? Funny how sometimes even the most useless things excite you the most when they are free, as in my case being a non-laptop owner, both the gifts meant nothing in terms of actual practicality. Anyways I followed the flow and stood in the line for breakfast. Not that I am much of breakfast eater but again free is the keyword . One thing I found to my liking was that, it was a hotel run by “coconut-oil-eating-south-Indians” to which category I belong and found that the food resonated with my taste-buds.

Anyways after the breakfast and exchanging pleasantries with my senior Niyas from TI, I found a seat to hear the keynote address from Derdre Handford Sr. VP of Global Technical Services, Synopsys and customer keynote from Behrooz Abdi Sr VP and General Manager CDMA Technologies, Qualcomm Inc. Most of the keynote was focused on Low power, a trend I later observed at Cadence TOT too. Personally, It was really nice to see a Iranian at the head of Qualcomm though I am not much experienced to know/not know that’s its common/uncommon.

Anyways, after the intro the people split into their different tracks. This is one thing I found odd. Since the attendance of the even was huge! The people were not fitting into a single hall anyway and all of them were accommodated by using different halls with video stream from the main hall. But still they did not divide the people based on track initially itself and so after common sessions, people needed to move between the rooms. I feel they could have divided the people initially it self based on track to their respective rooms to avoid such confusion.

Anyways coming to the “technical” details, the sessions were divided into panel discussions, synopsys tutorials, user papers and poster paper. Panel discussions were mainly focused on the theme of “low-power” so to speak. The rest were specific to the track and I can speak for the Synthesis and test track.  Most of the tutorials were focused on the Design Compiler – Topographical technology, which according to Synopsys is the next-big-thing in synthesis and there were a lot of user papers parroting the same.
“A paper titled Dynamic Shift Frequency Scaling Of ATPG patterns” from Open Silicon was a very good paper and it rightly won the best paper award. I think you can get more details at the SNUG India site

One of the strangest things was that on the first day, there was no chicken dish in the lunch (typically Indian eh?). Fish and mutton?? . Diner was looking good but I had to escape to my friend’s birthday bash.

So what were the takeaways?

• Got a overview of the DFT practice in India/Banglore , at least of companies that use Synopsys flow
• Companies include TI, Intel, Open Silicon, MindTree, Wipro etc
• Got an exposure to DFT-Topographical.
• Got an idea of focus areas for me to develop as a DFT Engineer.

On a side note I went to and Cadence Technology on tour the next week at Taj Residency Banglore. They were at least more sensible and gave out better timings as 8:30 reporting time and since the participation was lesser it seemed better organized. But since the only tool I use of cadence is LEC, wasn’t of much interest/ relevance to me. Their new SDC checker feature seems good as a lot of false paths can be identified and SDC redundancy can be removed. But it seemed like a logical extension of the technology rather than an innovative jump. Their free gift is currently gracing (or is it the other way around) my house in Kochi

BUT they were sensible and had chicken as a side course just in case you’re wondering