The popularity of this post ( most hits than any other post I think) can probably be put down to abundance of technical terms like 317 and 78XX in the article which are Googl’ed everyday.

The post was originally taken from my old website and I had lost all my images during that transition. Recently I was able to recover these images from my old hard-drive and do justice to the post

As you would find in most text books ( For Verilog I would recommend Samir Palnitkar’s Verilog HDL- A Guide To Digital Design and synthesis ), the different level of abstractions are behavioral, data-flow gate level and switch level. Enough has be written about them and I would recommend reading about them (LINK) Generally most code you write would be a combination of behavioral and data-flow styles of coding. What an abstraction provides is a different way to describe the hardware, which will be useful depending on the context.

It is very important to understand the philosophy/History behind HDL’s to use them. This is that there are two major motivations behind most HDL’s the two motivations are -:
1. To describe Hardware
2. To describe Hardware stimulus

This is a very simplistic view, but one I feel, that should be adopted initially. The basic problem with this is that, most people think only about the 1st motivation and assume that the synthesizer is some magic wand which will be able to construct hardware for any code we write. While this might be true in the future since we are moving more and more to algorithmic/behavioral level description of the hardware with higher level synthesis tools, with current Verilog and VHDL its not the case. Hence there is part of the language that is non-synthesizable What this means is that the some code that you write may not be automatically converted into equivalent hardware by the synthesizer. There are two reasons this

You are using the so called non synthesizable constructs in the language. To give a simple example, to model external stimulus or to model real behavior we can use “wait” command which is a delay command. But if we try to synthesize it, it will either give a error or a warning. It will give an error for a stimulus block since stimulus is a sequence of signals and their timing information and hence do not have any hardware equivalent and if we are using the wait to model delays within a module, the module will the synthesized and the delays ignored.

To understand this better lets see an example. Assume that you are writing a code that interfaces with an external EEPROM. Now once you write the code of your module you need to prove that it will work once we burn it on to a FPGA. To do this we move on to a phase known as “simulation” where the description we made of the hardware is used to model the behavior of our device. Now this will result in a Zero-Delay or Ideal simulation as all the constructs we use will happen instantaneously (but they will still be controlled by a generated clock and a sense of time will be there but the output of ,say, a inferred AND gate will be propagated instantaneously without accounting for the actual propagation delay in hardware) in the simulation where as when hardware works in FPGA, the delays will be present. Also since you need to interface to the EEPROM, you need to have a “Model” of the EEPROM to test your design against. This HDL model, which will be provided by the EEPROM vendor, will not contain the functional definition of the EEPROM but will be a behavioral model specified using actual observed delays (it can be best-case, worst-case or average delays depending on the model) so that it can be simulated. So here in this example, the module/block you write will be (should be) synthesizable where as the EEPROM will be a non-synthesisable model just for simulation. Also there will be a “test-bench” which will ensure that the correct connections between the modules are done and also any other external stimulus the two blocks requires are provided, for example your module might be controlled by a micro controller whose signals will be simulated by a micro-controller model within your test bench which will be a striped down model to give the control signals for your module. I hope this example makes the use of both styles of coding clear.

You are writing code that does not make sense from a hardware point of view. One common error is a doubly clocked flop or signals with multiple drivers.For example if you write code like

always @ (posedge clk or negedge clk)

it will throw an error while synthesizing. Why? From a C view this is fine since you are asking the always block to be activated at either of two events. But think of it from the hardware perspective
Consider the following code

always @ (posedge clk or negedge rst)
begin
if ( rst==0)
D<=1′=b0;
else
D <= Q ;
end

seeing this code a hardware engineer should see a simple D flip flop and not an if statement. Taking this analogy back to the earlier code you will see that you are asking the synthesizer to infer a doubly clocked flop which is not possible in hardware.

Another important problem that confronts a new HDL coder is called the “Synthesis-Simulation mismatch”. What this essentially means is that unless certain rules are maintained, the simulator will interpret and model what you write in a different way than what the actual generated hardware will behave like. This can lead to two cases, one in which the Simulation will work and actual hardware wont and vice versa. Both are dangerous since in the fist case your hardware wont work and in the second case you wont go to the hardware level as your simulation fails. This is generally due to small issues like leaving out signals from the sensitivity list etc. Instead of re inventing the wheel, I would suggest you read the paper [1] for a better understanding of this phenomenon

It is always encouraged that you have a very good understanding of how the simulator and synthesis process works to help eliminate errors. While should be the aim in the long run, adherence to some basic rules would help weed out most issues.

1. Always think about get an image of the hardware that you want to produce in your mind and then code it. Though it might seem really hard to do this the idea is not to think of all the hardware at once but to split the design into blocks of combinational logic followed by flops (Sequential design lends itself to this)

2. Always try to separate the combinational block and sequential blocks into different always/process blocks. This helps in debugging errors later and also simplifies coding

3. When modeling sequential logic, use non-blocking assignments. For reasons for 3-10 see [2]

4. When modeling latches, use non-blocking assignments.

5. When modeling combinational logic with an always block, use blocking assignments

6. When modeling both sequential and combinational logic within the same always block, use non-blocking assignments.

7. Do not mix blocking and non-blocking assignments in the same always block.

8. Do not make assignments to the same variable from more than one always block.

9. Use $strobe to display values that have been assigned using non-blocking assignments

10. Do not make assignments using #0 delays.

11. If you are having to use #1 delays read this Verilog Non-blocking Assignments With Delays, Myths & Mysteries

12. Use asynchronous resets wherever possible ( Being a DFT engineer I should not say this as it complicates DFT ). Read [3] To understand more.

13. If you are using state machines in your design read State Machine Coding Styles for Synthesis.

14. Try to avoid Dangling wires Due to misspelling (very common!) or unused signals, there might be dangling wires in the design. The synthesis tool might optimize these wires away.

15. Specify all conditions explicitly for ‘case’ Statement or “if else” Statements – To avoid problems with inferred latches

16. Understand the differences between ‘case’ vs. ‘if – else’ Statements – In general, case statements would translate to parallel muxes in hardware. Meanwhile, the use of if – else statements results in priority-based hardware, which can slow down the overall implementation of the design. Thus, only use if – else statement when priority-based hardware is required. Otherwise, use case statements to avoid possible inefficient implementation of the design.

17. When using an always statement to implement combinational logic, the sensitivity list has to include all signals that appear on the right hand side of the assignments inside the. This is to avoid synthesis simulation mismatches.

     

Finally but a very important time saver can be to try and get hold of a good Linting tool so that a lot of these errors and others are caught before going to the FPGA stage.

I hope that this was helpful and more comments/tips/questions are welcome.

References
[1] RTL Coding Styles That Yield Simulation and Synthesis Mismatches (SunBust Design)
[2] Non-blocking Assignments in Verilog Synthesis, Coding Styles That Kill!(SunBurst Design)
[3] Synchronous Resets? Asynchronous Resets?I am so confused!How will I ever know which to use?(SunBurst Design)

Do let me know if you guys think other links should be added.

It can be found @ eEDA Engineer’s Survival Kit

VLSI (FPGA) Project Topic Selection / List 

Like I promised earlier I am putting up some of the FPGA related projects which I feel can be taken up at college level.

I shall split them into 3 different types depending on infrastructure that’s required. Why I am doing this is because most of these projects would lend themselves to be coded pretty easily (comparatively) but it’s the infrastructure that required to get them working and SHOW that they are working on hardware that might become the stumbling block.

Simple Arithmetic

• Parity prediction in adders
• Protocol converters (eg:Manchester to UART)
• Multiplier
• 4 bit Processors
• CRC Generator
• Reed-Solomon Decoder

Since they are all Simple arithmetic  blocks , once coded they can be easily demonstrated in hardware using input switches and output LED’s that are present in most FPGA kits. Also the thing that should be kept in mind to keep their scale low (like a 4 bit word length for a processor rather than 8 bit) so that proving them on hardware is possible. If the scale increases it would be a bit hard to prove them on hardware since the pins of the FPGA are limited .You might have to think of innovative interfacing solutions like parallel to serial conversion inside the FPGA and reverse once outside using MSI shift-register chips etc

Protocols

• I2C (Master or Slave operation)
• SPI (Master or Slave operation)
• I2S
• JTAG
• UART

Here again the coding will not be an issue (not to take it lightly, but harder things are ahead) the stumbling block can be validation of the logic on FPGA. Since we need to be able to show that your chip is able to work seamlessly with the standard you would have to interface it with another device that operates in the protocol and prove that they can communicate. So along with the work on the HDL design you would have start working on the validation environment. Also interfacing, clocking etc would be harder. Also a logical oscilloscope can be very useful while debugging on hardware and access to one is an important criterion to select these kinds of projects

Application Based

• Image Watermarking on FPGA
• Traffic Signal
• Industrial Safely System
• Your Brilliant idea

In some ways, these are the safest projects to take. Here what you do is take a real life problem and solve it using electronics. You define the context of the pins and digital logic. Like a pin going high can indicate the activation of a safety latch to prevent a nuclear reactor from explosion Only difference between an ordinary electronic project and VLSI would be that the core logic that solves the practical problem would be implemented in FPGA. The actual logic to be implemented in the FPGA can be as simple as a string of ring counters or complex state machines depending on the problem that you are trying to solve AND how you propose to solve it. Also since the main idea is to (unleash your creativity and) get familiarized with FPGA flow and FPGA’s don’t lend into small form factors – a lot of packaging (“product-worthiness”)  related issues are sorted ,which would have arisen if the project had been done using components like micro-controllers and discrete components. (In the VIVA you can say that you are using the FPGA as a prototype and can go into mass production of smaller ASIC’S once the practicality is proved on FPGA )

As you can see my main aim was not to provide a comprehensive list of projects, which I feel is something that should be left to your imagination, but try to classify the projects based on the difficulties and infrastructure required so that you can make a informed decision which choosing the topic. I hope that this was helpful and please do leave a comment to share your experiences.

Project Considerations

Like I mentioned earlier a VLSI project is different for the different considerations that you must put in first as opposed to another “ordinary” project. If you do a FPGA based project, you are eliminating some of the issues existing with other type of VLSI projects like aligning with the foundry timing but still there are other important points. Here are some of the considerations that I feel must be well thought off before venturing into a VLSI project.

Facilities, Faculty and Tools

VLSI is a relatively new domain and hence this is one consideration that must go in earlier that other. Ask some questions to yourself

Who would be responsible for providing me with the FPGA Hardware?
In case its to be done your self, it can be a costly affair as a FPGA kit can cost over 30-40k Rs factor that in
In case it’s the college authorities, make sure that the FPGA kit is already available and also that’s its working properly. Most importantly check that someone knows know to use it at least in a rudimental fashion because otherwise you could end up spending a substantial time learning how to use the FPGA rather than doing the “actual” project. It is true that you would have to allocate sometime for learning the FPGA and to program it but it should only take up a reasonable amount of your total project time.

Who would be responsible for the software?
Like I said there would be two parts to the project. One is to be done at the software level (Major Part) and other at the hardware level. The software for the same can be very costly if you go for full fledged versions. In any case select the software to be used pretty early in the cycle and also try to go for software which has been used by someone you know so that there would be a quick resolution point for issues. Also Take at look at some of the free software that I have mentioned later.

Why not an External Agency?
In case you taking the help of a external agency ,  a training center or project center or going in for internship somewhere [Places I know that offer VLSI internships include ISRO, CEERI Pilani, IIT’s and IISc etc but you need to initiate the process very early ].  (for want of facilities or tools or faculty) Please make sure that you understand first itself what your level of involvement  in the whole project would be. It might do you good to have a completely working project done and delivered by them as far as marks as concerned by it wont do you any good once you come to the industry and you are expected to know certain stuff on account of you having done such a project already

Topic Selection

Another important thing to consider is the topic or the core of the project. Here people tend to be a bit extravagant with their choices. Understand that you are going into a new domain, learn a new language, learn new tools and then finally implement them. In case some part of this is already done, well you can go ahead and take “harder” projects but try not to bite too much than you can chew.

Personally I would recommend a “phased” approach. In this approach you take up a base issue say I2C. Then you look at the minimal features that need to be implemented, for example 7 bit addressing and just master mode or slave mode operation. This is what you should commit to the college also. Then if you are successful in doing this within your time frame you can go ahead and implement the advanced features. I will list some topics for consideration and my opinion on them later. (See part III)

Some Free tools and Links – :  (http://www.cs.iitm.ernet.in/~noorse/new/resources.html)

IRSIM Switch level Simulator
IRSIM is a tool for simulating digital circuits. It is a "switch-level" simulator; that is, it treats transistors as ideal switches. Extracted capacitance and lumped resistance values are used to make the switch a little bit more realistic than the ideal, using the RC time constants to predict the relative timing of events.

Netgen (Layout vs. Schematic)
Netgen is a tool for comparing netlists, a process known as LVS, which stands for "Layout vs. Schematic". This is an important step in the integrated circuit design flow, ensuring that the geometry that has been laid out matches the expected circuit. Very small circuits can bypass this step by confirming circuit operation through extraction and simulation. Very large digital circuits are usually generated by tools from high-level descriptions, using compilers that ensure the correct layout geometry. The greatest need for LVS is in large analog or mixed-signal circuits that cannot be simulated in reasonable time. Even for small circuits, LVS can be done much faster than simulation, and provides feedback that makes it easier to find an error than does a simulation.

Digital Standard Cells
This is an excellent source for LEF and GDS standard cells. The cells are all compatible with the MOSIS SCMOS rules for the various processes available through MOSIS (mostly TSMC and AMI, 0.18um to 0.5um).

VIS (Verification Interacting with Synthesis)
Verilog compiler (vl2mv) and logic verification. VIS (Verification Interacting with Synthesis) is a system for formal verification, synthesis, and simulation of finite state systems.

Logic optimization using SIS
This tool takes the BLIF format description and creates a reasonably good netlist representation using a set of standard cells described in the "genlib" format. SIS will do synthesis of both synchronous and asynchronous sequential circuits.

Verilog Compiler (Iverilog)
Icarus Verilog is a Verilog simulation and synthesis tool. Iverilog. (Latest)

Verilog Compiler (Iverilog) for Windows
Icarus Verilog is a Verilog simulation and synthesis tool

GTKWave (Electronic waveform viewer)
GTKWave is a digital waveform viewer useful for examining the output of various digital simulators (like Icarus Verilog, for example). It can read VCD, EVCD, LXT, and Synopsis output formats. It was built using the GTK+ toolkit.

Language Selection/Learning

This is another important decision to be made. Some of the important languages that you can use are Verilog, VHDL, SystemC, System Verilog etc.

For a normal engineering student with background in C there is a important distinction to be understood between coding in C and other software languages and HDL’s.  At one level most people emphasize that there is no concept of time in C and a different connect of parallelism. As far I see it even thought this is a correct way of stating the difference there is to be understood in a different way. This is something very important which will explain in another post.

As far as section is concerned SystemC and System Verilog have a lot of features which make it beneficial for verification so if you plan to place a lot of emphasis on verification and simulating (which you ideally should be but may not work within given timeframe). And of the two I think System Verilog is the language of the future.

As far as VHDL and verilog is concerned. Both are fine, but I have a bias towards verilog (even though I did my academic project in VHDL) mainly because I feel it is easier to learn that VHDL. VHDL in a sense is very structured which has a lot of uses when it’s a huge project, but in the structure it’s easier for a newbie to get lost.

Another Important point which is not stressed at the college level (at least mine) was the power that a scripting language can provide. If your working on Unix Shell it self would be enough and TCL is a good choice in Windows environment (and Unix too). If some of the tasks can be automated, a lot of time can be saved and also final presentations can be given that “professional” touch. But you have to objectively plan whether usage of a new language would save time or waste it ???

Project Planning

As is often said (but not done enough) Prior Planning Prevents Poor Performance. Planning is a very important phase of any project let alone one such as this. Also try to factor in as many risks as possible. End of the day remember that even seasoned managers get planning wrong but still the project goes ok. Just remember that it’s a facilitator than the deliverable. Some of the phases that must be considered include

1. Ramp-Up VLSI Basics/Coding – Must be done as soon as possible and should reach a reasonable level of comfort here by writing smaller projects
2. Ramp-Up Hardware – Must be done as soon as you get your hands on the hardware. Try to implement smaller things like counter etc and see the LED’s blinking
3. Design Phase – Try to visualize the whole project to be split into parts that can be independently coded and tested. Not all parts may be possible but as a general rule try to visualize the hardware before writing it. A study of designing writing good state machines (if required) is good. 
4. Coding Phase – This is some of the phases that can be sped up. Try to the capabilities of the tool to maximum. For example some tools might write out and give simple structures like FIFO etc. Unless the project is too simple and there are just FIFO’s and simpler stuff try to use the tool for the same. Make sure you understand all the code the tool generates except for maybe some macros etc.
5. Verification – All individual modules should be verified by subjecting it to simple test-cases. Ideally as soon as you start coding you project, someone else (other than the coder) should start on a test bench to test the code that is being written. Ideally both should not communicate with each other how they are implementing their work and should take all information from the specifications document detailing the specification. The idea is that if the person developing the testing environment and test cases come s to know of the intricacies design, he might get subconsciously biased and a true verification might not take place. How much of this is actually possible is something should be decided based on different constants that are on a academic project.
6. Some level of automation using scripting languages, if pre-planned can save a lot of time

Documentation

I know from a personal perspective that documentation can be a pain in the wrong place. But if you have a rough document where you pen down your experiences, it can be very helpful while making a final formal document. It has other uses like being helpful for other team members and also for your juniors.

Some Other Ideas

Also if you are really interested some other ideas include

1. Study Group – In case more than one team is doing different VLSI projects, a study group within the college would be very beneficial for all the teams. It might help not to  re-invent the wheel , so to speak , if there is proper communication between the teams both at the learning phase and also at the implementation phase
2. Another thing that can make things interesting is to start up a blog to document your experiences. This is true for any kind of project though. It is generally very common outside India I believe. It can help other doing similar work to discover you and ask for help or help you out. We had done something simlar, but our laziness got the better of us FreeCan

I hope this is helpful in your endeavor and do let me know of your experiences- successes and un-successes (there are not nothing as failure as long as you learn a few new thing….which I am sure you will) and don’t hesitate to contact me for any help you think I can provide

Continue reading Part III 

But the trouble is that, like with any electronic projects (not to belittle any software engineers as a software project also lends to similar difficulties) is that, conceiving the idea is one thing but getting it working in a satisfactory manner is a altogether different thing. And especially since VLSI domain is a comparatively new one, with hindsight, I believe that there are some things that need to be understood/ considered by the person before jumping into the world of VLSI. I am going to try to pen down these concepts/ considerations as a starting point for people trying to do the same.

Two Faces

Chip design is, in a very broad sense, two part affair. The first part of the design life cycle purely exists on a computer. At this sage you are designing your whole system, coding it, simulating it, and testing it etc in a computer using suitable software. This is true whether it Analog or Digital or FPGA or Custom ASIC. Once this stage reaches a decent enough level of maturity then the outputs from this state is “transferred” to Silicon. How and when this is done is dependent on what kind of a chip you are making.

Analog

When you talk about VLSI, it includes both analog and digital parts. I am a digital engineer and hence won’t be able to comment much on the Analog Projects. But still there are some concepts that are common which I shall explain. Like I said earlier, the first part of the design cycle is carried out entirely inside a computer. For analog and digital it would be different tools. I believe that analog uses tools like SPICE etc for doing transistor level simulation. Once this phase is over the output might be in for a mask file which will then need to be given to a foundry (in case of analog and custom ASIC) using which they will manufacture the chip and give it back to us.  I am not aware of any analog foundries that would take up work for academic projects.

Digital

Digital chips can be widely classified into Custom ASIC and Field Programmable

Custom ASIC

Its not proper terminology but for the purpose of this discussion I shall refer to all digital Chips that require to be manufactured at the foundry as Custom ASIC. If you know basic VLSI theory (Which I strongly suggest you learn if you are panning to do such a project ) you will understand that the manufacturing processes of ASIC’s involve a large number of “masks” that aid in the manufacture of the desired transistor -> gate structures. Depending on the number of masks that are programmed by the end user we can have different types of Chips which are a result of a trade-off. The more masks you can program, the more control you have over the logic and more efficient you chip but this is met with increasing costs too. In custom ASIC’s we have either no or only some of the mask’s being predefined, hence allowing greater programmability. For a more exhaustive discussion on this matter please refer John Smith’s excellent book or similar books.

Since these chips allow more programmability, they need to be designed at the transistor level or gate level using suitable software like MAGIC and then the masks that are the output need to be given to the foundries that would manufacture and give the chip back. Since you would be operating at the transistor level you can do only functionally very simple projects in this manner. Another option is that the foundries would give you their library cell definitions and you would have to write RTL (HDL) and “synthesize” netlists using these library components. You would then have to do layout and “close” the timing (remove volitions) and give that mask to the foundry. But this can be very hard to do due to non-availability of tools and also due to want of know-how

Semiconductor Complex, Chandigarh (Thanks to my friend Vaibhav Mathur )  is one such foundry in India. They also undertake academic projects between certain periods of time. This needs to be carefully considered while going in for a project. Also since you are starting at the transistor level and the level of abstraction is minimal, you need to take up seemingly simple projects, at least from the functional point of view.

Field Programmable

As their name suggests, they can be programmed from the comfort of ones home or college (some comfort eh?). You can possibly guess that we that lesser number of masks are programmable, i.e. the interconnect masks, the rest of the masks have special structures (ROM based or Look-Up Table based) that make this kind of programming possible. FPGA’s are one type of these chips with others including CPLD, PSoC, PLA, PAL etc

From a normal Indian college (that I came from) perspective this one of the most practical type of project to choose and also I did my main project on FPGA so I would be discussing more about it.

Continue reading part II

One of the basic powers of UNIX based systems comes from the fact that there are a gazillion ways of doing even the simplest of tasks. With the combined philosophies of KISS and “Small is beautiful” implemented beautifully along with the pipelining and I/O redirection, the power can actually be overwhelming at times. This is exactly a stumbling point for a person new to this world, especially if he’s coming from the “click-click-click” philosophy of windows. Agreed, the latter philosophy is best suited for a general user who uses computer sparingly or for tasks such as browsing and chatting. The typical “Non-IT” portfolio.  But for an EDA engineer (like me) or a power user to think of a world without these tools is blasphemy. Still with so many choices available, a lot of people who would love to have the power dither away from the “right” path due to a sense of vastness.

I have held the view that languages are just means to end. Writing a program is not the hard part, its just the unavoidable detail.Any person with reasonable intelligence can use the IT industry mantra of {“CTRL+C-CTRL+V”} and write reasonable code. This is particularly true in the case scripting as the “hard” part such as memory management etc is removed. Hence we see that in the scripting mindset the focus is to get the job done and ask questions about efficiency etc later (unless it’s a heavily executed script and the current implantation is VERY bad). So the most important part of scripting boils down to the language/tool selection which can be a daunting task, taking the amount of choices available. Even though there can never be hard and fast rules , I thought I would pen down some thumb rules that can be applied to make this daunting task easy.

Never start with NO!
First thing to understand is that -: always be open to change…..but with intelligence. Don’t choose a language just because you’re comfortable with it. Even though there are exceptions to this rule like when time is playing a very important parameter in determining the value of the current solution or the complexity reduction offered to your with the new language does not justify the extra effort to be spent to get the thing implemented(Remember that the product of this first effort can be later used if the code is modularised) . I know this sounds vague but the idea I want to convey is that always consider other languages before committing to a particular language.A general flow for choosing a language is given at the end.

Visualize the Solution
Get a grip of the capabilities of the language rather than spend too much time learning the each and every syntax. More often than not, the time difference between when you learn the language and when you have to solve a practical problem would be too much that the intricacies that you spend hours learning would seen as distant to you as the basic syntax. Instead if you get the capabilities they it will help you visualize the solution in a particular language and the dirty stuff can be dealt with later. Chances are that most of the “challenges” that you have to face while implementation would have been faced by hundreds before and would be well documented so just GOOGLE!

Modularize it!
This is something I try to implement all the time. Once you visualize your solution, split it into independently implemental chunks. Not only does this help you write code that’s easily understandable/maintainable/modifiable but it also helps reduce your work when you are writing another script if you can reuse some of the modules.

Hybrids/ Genetic engineering is good.
Ever read about the plants that have insecticide genes engineered into them? Similarly , it might make sense to implement a part of the solution in one language and the other in another. As long as you can easily understand the way the data is to be transferred between the two parts, Go for it!

The following rules/questions can be used as a guideline while choosing the language.

It’s a simple solution involving a lot of individual UNIX commands / executables
Can I see the solution in Shell?

It involves rudimentary text processions, like single character substitution and some character removal
Can I see the solution with Shell along with cut and tr commands?

It involves more complex text manipulations
Can I see the solution in Shell and SED?
(AWK can do a log of things SED can do, but complex stream editing is something SED is better at (faster, the code is terser, etc.) but SED has no function and no arthemetic)

I also want some multilevel text manipulations and with support for variables during these complex text manipulation steps.
Can I see the solution in Shell and AWK?

It involves large scale text manipulation and reports parsing.
Can I visualize the solution in PERL? (or Python?)

It involves automation of interactive software like ftp, ssh etc
Can I see the solution with Expect along with a host language like TCL?

Please do leave a comment if you feel that there is anything else that you have come across that can make this more helpful. 

http://www.kilala.nl/Sysadmin/script-variablescope.php

(Please do not proceed without understanding the actual issue since I stand a chance of being grossly misinterpreted otherwise)

Dear Diary,

Today she (bash) behaved very badly with me. Like I have been telling you lately, She has been acting very strange. It’s like she’s a totally different person. Every day she comes up with more and more mood swings (modes via command switches) particularly while dealing with others that work with her (programs). Gone are the days when she knew what I wanted and I knew how to get it from her. The more I have gotten to know her, the lesser I have understood about her vagaries.I know I can’t interface with her as well as they (programs) do and I accept that but all I ask for  is  a little bit of consideration for my feelings. Is that too much to ask? But she’s not at all bothered of my feelings, telling that I am jealous and paranoid since it’s not her mood but her colleague’s (programs)   with whom she has to deal with (run). But I feel its cuz shes behaving so freely with them and giving them so much "permissions" (its a ubuntu system )

But today something happened, that really turned her argument on its head. I was playing around with her (for a) "while" and was pipeing some data into her "while" (construct). Everything was working fine while I was inside her, but the moment I got out, it was as though everything changed. She has no memory of me and all the things I had did inside her. Half an hour of work and no final effect and I actually thought she was enjoying it. I was very frustrated and did it again and again, but to the same tune.

After that I finally decided to ask around and would you believe it? Others know her better than Me . It seems her “while” is a separate person, like her inner child or something, and it transforms her into someone else (sub-process) and what ever I pipe into her is lost the moment I get out

Are all she(ll)s in this world two faced?

Good night

Ok so what is it?
Software defined silicon is a new electronic device that is both low cost and easy to program.
 
At an abstract level, How is this different from existing ASIC/FPGA?
This is actually two questions. Traditionally Full/Partial custom ASIC is less costly that FPGA per unit when the volumes increase) where as FPGA is more suited for prototyping since the time taken for design changes to be translated to hardware is much lesser. So while choosing between FPGA and Custom ASIC is a trade-off between cost and programmability

SDS will offer the better programmability than FPGA at a much lesser cost than FPGA with lesser lead times and also in a single language (C)

At a abstract level, How is this different from existing micro processors?
Microprocessors are general purpose chips. They are designed with the traditional single threaded flow in mind. SDS can be called a "events-driven processor engine". An events-driven processor is one that is capable, when an event occurs, of executing software immediately, and then terminating, and waiting for the next event. The events are things like a pin changing state.
So it you would be able to write really "real-time" software whose performance can compare that to hardware. For example you can write real time communication protocol that’s traditionally implemented in hardware in software. Also in the creators own words “So we’ve taken a very responsive, fast, deterministic, real-time processor engine, and we’ve integrated into that very tight pin control”, says Hurley, “and we’ve developed a core-to-core communications interface. So now we can build arrays of cores that can control pins.”

Isn’t RTL similar to C?
At syntax level both are high level languages. But while writing RTL we need to be mindful of what hardware our code is going to infer so at the conceptual level its very different from C.

In one word?
“You’re implementing functionality that’s traditionally implemented in hardware in software”

How is the cost low even with better features?
From the silicon cost point of view, XMOS is using processors, which are silicon efficient, and RAM, which is the most silicon efficient structure. By using processors and RAM, it gains big cost advantages.

What about an example of development freedom?
“The development freedom the customer has is incredible because the customer can choose how to partition that capability”, says Hurley, “what’s really powerful is that a customer has a budget of processor cycles, he can choose how to spend that budget on real-time tasks such as interfaces, DSP, and control, and, more importantly, he is then able to dynamically alter that so, when they’re doing multiple products (typically consumer companies have a general platform supporting 20 or 30 products) he can choose to say: ‘I don’t want a UART in this design, but I do want to run an MP3 decoder. So I will remove the UART piece of code, and I will re-purpose those processing cycles into my DSP capability. I don’t believe anything in the market today can offer that level of capability to a customer.”

What does this mean for hardware engineers?
If this was to become the chip that survives the current war between FPGA /ASIC/PSoC/SDS , the hardware engineers outside this technology would starve

What does this mean for the software engineers?
They get more power as they can write more powerful code that can at a lot of level emulate hardware perfectly, Something that was not possible till now

What’s the different with respect to the design flow?
Usually the hardware flow would involve work on EDA software that would design the hardware to be implemented. The coding at this stage is usually done in RTL like verilog/ VHDL. Then if the hardware so implemented included processors software would be written run on the processor.
Here in SDS the design at the hardware level is generic. the resource you have is processor cycles that you can allot via your programming (in C with some additions for defining port structure and using multi-threading and parallelism) to the task to which you want to allot it to. So RTL coding is removed out of the flow.

"It’s a standard embedded software development flow starting with C/C++ source, compile, link, assemble and de-bug using standard industry development tools."

Ok what all can it currently do?
"SDS can run Ethernet MAC and the MII interface in software at 200Mbps, it has DSP capability and control capability"

Now how can I call it a COMPLETE year without attending one the Major calendar events in every EDA-using engineer’s year? Yep….this feeling was so strong that I finally registered for SNUG and Cadence Technology on tour and ended up attending them as well.  Here is what I thought of both

SNUG 2007

For the uninitiated,  SNUG stands for SyNopsys User Group and it is a yearly conference for users of synopsys tools (Synopsys being a major EDA tool vendor with Cadence Mentor Graphics and Magma being the other biggies). In hindsight, the turn-out was really good. Also, for me, working primarily on the synopsys tools, the organization of the tracks made sense. Tracks are basically parallel programs sessions specific to domain of the engineer. For synopsys its organized as “Physical Design & SignOff”, “Synthesis and Test”  and least but miles ahead of least (No I am not a verification engineer ) the “Verification and AMS” track. Since a lot of work in India takes palace in the verification field (so I am lead to believe), this track generally attracts the biggest crowds with “Synthesis and Test”  having the lowest participation.

We were asked to reach the place at around 7:15 ( Were they bonkers I wonder?) at Leela Palace and for a morning hater like me this was a pressure-point….but I managed to reach there by 8:30, pretty good considering it was still MORNING The registration was pretty hassle free as the kit and ID cards were already prepared for the pre-registered people and were set up in alphabetic order. We just needed to show our ID card to get the same. I knew that these EDA vendors are pretty generous with gifts but was really surprised to find a USB Mouse!!! and a Laptop Light!!! along with the kit. Not a total waste already eh? Funny how sometimes even the most useless things excite you the most when they are free, as in my case being a non-laptop owner, both the gifts meant nothing in terms of actual practicality. Anyways I followed the flow and stood in the line for breakfast. Not that I am much of breakfast eater but again free is the keyword . One thing I found to my liking was that, it was a hotel run by “coconut-oil-eating-south-Indians” to which category I belong and found that the food resonated with my taste-buds.

Anyways after the breakfast and exchanging pleasantries with my senior Niyas from TI, I found a seat to hear the keynote address from Derdre Handford Sr. VP of Global Technical Services, Synopsys and customer keynote from Behrooz Abdi Sr VP and General Manager CDMA Technologies, Qualcomm Inc. Most of the keynote was focused on Low power, a trend I later observed at Cadence TOT too. Personally, It was really nice to see a Iranian at the head of Qualcomm though I am not much experienced to know/not know that’s its common/uncommon.

Anyways, after the intro the people split into their different tracks. This is one thing I found odd. Since the attendance of the even was huge! The people were not fitting into a single hall anyway and all of them were accommodated by using different halls with video stream from the main hall. But still they did not divide the people based on track initially itself and so after common sessions, people needed to move between the rooms. I feel they could have divided the people initially it self based on track to their respective rooms to avoid such confusion.

Anyways coming to the “technical” details, the sessions were divided into panel discussions, synopsys tutorials, user papers and poster paper. Panel discussions were mainly focused on the theme of “low-power” so to speak. The rest were specific to the track and I can speak for the Synthesis and test track.  Most of the tutorials were focused on the Design Compiler – Topographical technology, which according to Synopsys is the next-big-thing in synthesis and there were a lot of user papers parroting the same.
“A paper titled Dynamic Shift Frequency Scaling Of ATPG patterns” from Open Silicon was a very good paper and it rightly won the best paper award. I think you can get more details at the SNUG India site

One of the strangest things was that on the first day, there was no chicken dish in the lunch (typically Indian eh?). Fish and mutton?? . Diner was looking good but I had to escape to my friend’s birthday bash.

So what were the takeaways?

• Got a overview of the DFT practice in India/Banglore , at least of companies that use Synopsys flow
• Companies include TI, Intel, Open Silicon, MindTree, Wipro etc
• Got an exposure to DFT-Topographical.
• Got an idea of focus areas for me to develop as a DFT Engineer.

On a side note I went to and Cadence Technology on tour the next week at Taj Residency Banglore. They were at least more sensible and gave out better timings as 8:30 reporting time and since the participation was lesser it seemed better organized. But since the only tool I use of cadence is LEC, wasn’t of much interest/ relevance to me. Their new SDC checker feature seems good as a lot of false paths can be identified and SDC redundancy can be removed. But it seemed like a logical extension of the technology rather than an innovative jump. Their free gift is currently gracing (or is it the other way around) my house in Kochi

BUT they were sensible and had chicken as a side course just in case you’re wondering