a mARTIAN dIARY

I was recently helping one of my juniors search for a seminar topic and I came across the idea of SDS (Software Defined Silicon). The following is some questions that where thrown at me while I was explaining it. A bagful of thanks to David Manners for his excellent article. Since the net is my primary source of information for me regarding this technology there might be mistakes in my understanding, so if you find any please leave a comment so that I can rectify it

Ok so what is it?
Software defined silicon is a new electronic device that is both low cost and easy to program.
 
At an abstract level, How is this different from existing ASIC/FPGA?
This is actually two questions. Traditionally Full/Partial custom ASIC is less costly that FPGA per unit when the volumes increase) where as FPGA is more suited for prototyping since the time taken for design changes to be translated to hardware is much lesser. So while choosing between FPGA and Custom ASIC is a trade-off between cost and programmability

SDS will offer the better programmability than FPGA at a much lesser cost than FPGA with lesser lead times and also in a single language (C)

At a abstract level, How is this different from existing micro processors?
Microprocessors are general purpose chips. They are designed with the traditional single threaded flow in mind. SDS can be called a "events-driven processor engine". An events-driven processor is one that is capable, when an event occurs, of executing software immediately, and then terminating, and waiting for the next event. The events are things like a pin changing state.
So it you would be able to write really "real-time" software whose performance can compare that to hardware. For example you can write real time communication protocol that’s traditionally implemented in hardware in software. Also in the creators own words “So we’ve taken a very responsive, fast, deterministic, real-time processor engine, and we’ve integrated into that very tight pin control”, says Hurley, “and we’ve developed a core-to-core communications interface. So now we can build arrays of cores that can control pins.”

Isn’t RTL similar to C?
At syntax level both are high level languages. But while writing RTL we need to be mindful of what hardware our code is going to infer so at the conceptual level its very different from C.

In one word?
“You’re implementing functionality that’s traditionally implemented in hardware in software”

How is the cost low even with better features?
From the silicon cost point of view, XMOS is using processors, which are silicon efficient, and RAM, which is the most silicon efficient structure. By using processors and RAM, it gains big cost advantages.

What about an example of development freedom?
“The development freedom the customer has is incredible because the customer can choose how to partition that capability”, says Hurley, “what’s really powerful is that a customer has a budget of processor cycles, he can choose how to spend that budget on real-time tasks such as interfaces, DSP, and control, and, more importantly, he is then able to dynamically alter that so, when they’re doing multiple products (typically consumer companies have a general platform supporting 20 or 30 products) he can choose to say: ‘I don’t want a UART in this design, but I do want to run an MP3 decoder. So I will remove the UART piece of code, and I will re-purpose those processing cycles into my DSP capability. I don’t believe anything in the market today can offer that level of capability to a customer.”

What does this mean for hardware engineers?
If this was to become the chip that survives the current war between FPGA /ASIC/PSoC/SDS , the hardware engineers outside this technology would starve

What does this mean for the software engineers?
They get more power as they can write more powerful code that can at a lot of level emulate hardware perfectly, Something that was not possible till now

What’s the different with respect to the design flow?
Usually the hardware flow would involve work on EDA software that would design the hardware to be implemented. The coding at this stage is usually done in RTL like verilog/ VHDL. Then if the hardware so implemented included processors software would be written run on the processor.
Here in SDS the design at the hardware level is generic. the resource you have is processor cycles that you can allot via your programming (in C with some additions for defining port structure and using multi-threading and parallelism) to the task to which you want to allot it to. So RTL coding is removed out of the flow.

"It’s a standard embedded software development flow starting with C/C++ source, compile, link, assemble and de-bug using standard industry development tools."

Ok what all can it currently do?
"SDS can run Ethernet MAC and the MII interface in software at 200Mbps, it has DSP capability and control capability"

So I am about to finish my first year as an EDA engineer. It does put me a scale up in terms of being an engineer with 1 year industry experience. Hurray(?)!!!.

Now how can I call it a COMPLETE year without attending one the Major calendar events in every EDA-using engineer’s year? Yep….this feeling was so strong that I finally registered for SNUG and Cadence Technology on tour and ended up attending them as well.  Here is what I thought of both

SNUG 2007

For the uninitiated,  SNUG stands for SyNopsys User Group and it is a yearly conference for users of synopsys tools (Synopsys being a major EDA tool vendor with Cadence Mentor Graphics and Magma being the other biggies). In hindsight, the turn-out was really good. Also, for me, working primarily on the synopsys tools, the organization of the tracks made sense. Tracks are basically parallel programs sessions specific to domain of the engineer. For synopsys its organized as “Physical Design & SignOff”, “Synthesis and Test”  and least but miles ahead of least (No I am not a verification engineer ) the “Verification and AMS” track. Since a lot of work in India takes palace in the verification field (so I am lead to believe), this track generally attracts the biggest crowds with “Synthesis and Test”  having the lowest participation.

We were asked to reach the place at around 7:15 ( Were they bonkers I wonder?) at Leela Palace and for a morning hater like me this was a pressure-point….but I managed to reach there by 8:30, pretty good considering it was still MORNING The registration was pretty hassle free as the kit and ID cards were already prepared for the pre-registered people and were set up in alphabetic order. We just needed to show our ID card to get the same. I knew that these EDA vendors are pretty generous with gifts but was really surprised to find a USB Mouse!!! and a Laptop Light!!! along with the kit. Not a total waste already eh? Funny how sometimes even the most useless things excite you the most when they are free, as in my case being a non-laptop owner, both the gifts meant nothing in terms of actual practicality. Anyways I followed the flow and stood in the line for breakfast. Not that I am much of breakfast eater but again free is the keyword :P. One thing I found to my liking was that, it was a hotel run by “coconut-oil-eating-south-Indians” to which category I belong and found that the food resonated with my taste-buds.

Anyways after the breakfast and exchanging pleasantries with my senior Niyas from TI, I found a seat to hear the keynote address from Derdre Handford Sr. VP of Global Technical Services, Synopsys and customer keynote from Behrooz Abdi Sr VP and General Manager CDMA Technologies, Qualcomm Inc. Most of the keynote was focused on Low power, a trend I later observed at Cadence TOT too. Personally, It was really nice to see a Iranian at the head of Qualcomm though I am not much experienced to know/not know that’s its common/uncommon.

Anyways, after the intro the people split into their different tracks. This is one thing I found odd. Since the attendance of the even was huge! The people were not fitting into a single hall anyway and all of them were accommodated by using different halls with video stream from the main hall. But still they did not divide the people based on track initially itself and so after common sessions, people needed to move between the rooms. I feel they could have divided the people initially it self based on track to their respective rooms to avoid such confusion.

Anyways coming to the “technical” details, the sessions were divided into panel discussions, synopsys tutorials, user papers and poster paper. Panel discussions were mainly focused on the theme of “low-power” so to speak. The rest were specific to the track and I can speak for the Synthesis and test track.  Most of the tutorials were focused on the Design Compiler – Topographical technology, which according to Synopsys is the next-big-thing in synthesis and there were a lot of user papers parroting the same.
“A paper titled Dynamic Shift Frequency Scaling Of ATPG patterns” from Open Silicon was a very good paper and it rightly won the best paper award. I think you can get more details at the SNUG India site

One of the strangest things was that on the first day, there was no chicken dish in the lunch (typically Indian eh?). Fish and mutton?? :P. Diner was looking good but I had to escape to my friend’s birthday bash.

So what were the takeaways?

• Got a overview of the DFT practice in India/Banglore , at least of companies that use Synopsys flow
• Companies include TI, Intel, Open Silicon, MindTree, Wipro etc
• Got an exposure to DFT-Topographical.
• Got an idea of focus areas for me to develop as a DFT Engineer.

On a side note I went to and Cadence Technology on tour the next week at Taj Residency Banglore. They were at least more sensible and gave out better timings as 8:30 reporting time and since the participation was lesser it seemed better organized. But since the only tool I use of cadence is LEC, wasn’t of much interest/ relevance to me. Their new SDC checker feature seems good as a lot of false paths can be identified and SDC redundancy can be removed. But it seemed like a logical extension of the technology rather than an innovative jump. Their free gift is currently gracing (or is it the other way around) my house in Kochi

BUT they were sensible and had chicken as a side course just in case you’re wondering

As I pointed out here of how Features are acquired…..

The big 4 in EDA are trying to be the first to the DFM market by buying out the smaller specialist companies in the DFM field.

Now it is Mentors Graphics turn

Mentor buys 45nm chip design tool firm

Mentor Graphics has acquired Sierra Design Automation a supplier of place and route semiconductor fabrication tools for 65nm and 45nm process nodes.

The reason behind the acquisition is the need to address the range of process technologies and new design for manufacture (DFM) methodologies which are expected to influence next generation chip designs.

Earlier it was Cadence

 Its fun watching a industry evolve  and be in it rather than read about something that happened before you were born

http://www.eetimes.com/news/design/showArticle.jhtml?articleID=199901924

Really good statement from a person I am starting to admire, Rajeev Madhavan, CEO of magma….
What he says about the IP’s getting integrated with the EDA tools seems to be correct; I mean the way I see its virtually important for single-IP based startup’s to come up. To compete with the abundance of so called "infrastructure" IP pool that the big player’s have. See, what’s the point of a single IP company with expertise in DSP spending time/money developing buying infrastructure IP like IIC and SPI and trying to integrate it into their environment? I would always buy it from the tool vendor provided he gives me a plug-in solution to my environment and also to me at a competitive rate. I know with the technology purists there is some resentment to club IP vendors with EDA industry,but from what I have gathered, we are moving into a area where IP would make a substantial section of the EDA tool’s profit and it doesnt ake sense for me not to leverage on a earning oppertunity as long as it does not affect your work in your core competencies and may even fund more research in the Core business of EDA and talking of the crowd, wouldnt at least some of the people who buy the tools be also in a position to dictate the IP buying for their respective companies? Since I have not attended DAC I cant comment, but I feel probably yes….

Coming back to the heading of the post, in the shark eat fish world of EDA industry….this statement….so well sums it up

Me and my best buddy Zubin, who’s a fanatic RedShite supporter, have this habit of trying to find analogies with the football world ,actually the English premiership, and the everything else in life, and while trying to explain the EDA industry to him ( him being totally clueless as he’s from the ERP field), he came up with a interesting analogy
 The EDA companies investing in their own R&D is like the clubs investing in their academy, there is a remote chance of getting a Rooney or a Gerrad ( which would be a break through idea like Custom wire load models  ? ) but chances are less….mostly you end with a squad player like Tony Hibbert ( which in EDA terms would be some flow development/refinement, which would seamlessly integrate the different tools or flow reference model etc)  who is none the less very important for the success of the team (the tool) . And  some club like Wolves would come up with Joelen Lescott (in EDA terms some geek graduate from college would come with the next big Idea of, say,  DFM (design for manufacturability)), but the club wont achieve anything because he alone cant will them matches ( the DFM idea wont survive on its own) and would be brought by the big club ( would be brought by Cadance for example…integrated to their flow to make a world class product) and the club would win the Champions league ( successful chip tapeout perhaps :P) ….
 To add my own parts to it
 Categories create companies (different clubs have different type of playing like arsenal and Manu for one touch football and Chelsea playing the direct approach and Everton with the work-rate based play) Features get acquired ( features are key players with key skills that are either acquired or developed in-house) but the company has to think properly to look at what to acquire, not only just how good the idea is but also how well it suits their category ( not look at just how good the player is but also that his skills are what the team needs or u will end up being Arjen Robben at Chelsea, a brilliant player WASTED)
 
anyway I have kept all the beautiful people in my dreams waiting today for too long……

Good night and Au revor Kochi

• Moore’s Law : The number of transistors on a chip doubles annually
• Rock’s Law : The cost of semiconductor tools doubles every four years
• Machrone’s Law: The PC you want to buy will always be $5000
• Metcalfe’s Law : A network’s value grows proportionately to the number of its users squared
• Wirth’s Law : Software is slowing faster than hardware is accelerating 

Except for Machrone’s law I feel everything stikes a chord within me….but I guess if you always go for the latest most bestest and garandanglus (if thats a word) that would also hold true….not for cheapos like me who go for second hand computer models

 From “5 Commandments”, IEEE Spectrum December 2003, pp. 31-35