a mARTIAN dIARY

One of the worries that older generation of India fret about is of, what they see, as a general decline in values and culture. For them Inter-Caste marriages take the cake when looking at such indicators of decline. Of course a treatment of this subject by the hands of an old-school Indian can only find it to be outright wrong and a treatment from the progressive school of thought would give it kudos. The first group’s opposition can be termed irrational and the second group also don’t back their claim on scientific data as to why is it “better”. Also the second group does not leave any room for the justification of the practice of intra-caste marriage at any point of time in our history as they see it as one of the all time “evils”. But this is inconsistent with scientific models as nothing can come into existence by happenstance The problem with most of these analysis is that the causes are put down to religion/caste structure and they do not probe deeper into the real causes, which I am going to try and do.

In the Darwinian model, the reason for most social interactions comes from the concept of the selfish gene. For those who cam in late, the concept of The Selfish Gene advocates that most social customs starting from religion to altruism can be traced back to the need of the gene to survive the filtering that happens during each generation.In line with this the two main processes by which the gene (note it is the gene and not the organism) survives is by kinship and reciprocal relationships.

As is obvious, the kinship concept is the one that can be observed in the intra-caste marriages, pooling similar genes together and giving that gene a better survival rate as the people of similar kin would stick together. But this is a micro level condition for the survival of the gene. The consideration at the macro level is that the society, which again exists due to reciprocal relationships between people of different castes/genes, should be structured in such a way that as a whole, it is capable of surviving. Since in the past the nature of work was directly linked to the household/caste into which you are born, intra-caste marriages were the most acceptable to the gene as it would help hone the similar attributes within the similar caste, helping it become more and more “evolved” for the job and hence help in the survival of the society as a whole as long as people played out their proper roles.

But as times have changed, the work done (also seen as the contribution made to society) is no longer linked directly to birth. ( This shift maybe seen as a long term strategy of the gene as it realises about threats that are more relevant in a ever shrinking world like a fatal bacteria/virus that can wipe our humanity or problems from the heavens) And consequently there is not much point for the gene at the macro level to favour intra -caste marriages as honing and concentrating the skill-sets within the same caste/race is not helping the society at a macro level. With globalisation coming and move towards a knowledge based economy, older important traits like the ability to digest food from a particular area and of brute physical strength has started getting replaced with other traits like intelligence and adaptability as far as mate selection goes. On the basis of this, the fact that liberal girls like to have “fun” with physically dominant men but settle with stable men with jobs can be put down not just to the financial stability the latter brings, but the also to the important position intelligence is getting in breeding for the next generation. The initial “fun” phase can in a similar way put down to a residue of the old system. Also in similar line, cross breading between castes and races can be seen to facilitate the evolution of the next superhuman who can eat from anywhere and face bacteria from any part of the world and still survive.

So with more importance or chances of survival being associated with a person with lineage in different caste and races, inter-caste marriage and inter-race marriages can be put down as the next step of evolution rather than degradation in culture.

As a side note a rational approach should also be maintained to other facets of marriage also. For example the early days, we did not have a government to give us tax benefits for investing money and so investment was certainly not seen as the primary avenue for spending money. Hence our forefathers, more my foresight rather than chance, invented customs that serve the same purpose. Take for example the custom of buying gold for marriages / dowry system. From a rational view point it can be seen as a kind of investment for the future for the well-being of the couple. And it is quite possible that the astrological good seasons and bad seasons for marriage would be linked to how the old global gold markets fluctuated among other things. But as time has passed the original intent seems to have been forgotten by people (as in the case of a lot of customs) and it has been reduced to a mere ritual and in fact has turned counter productive as now “marriage season” is the peak of the gold cost curve. So the next time you go to buy gold for a marriage when the gold price is high, just think of the stock trader who buys high and sells low

(A  HUGE! thanks to Miss R for pointing out some silly silly mistakes ! :)  )

The rhythmic cranking of the old Khaitan fan is my company as I wait for Mr Krishnan Nair. KrishnEttan (Ettan meaning big brother in Malayalam) , as he is fondly called, is an old friend of my father. As I look around, I find myself sitting in a not-so-unfamiliar Kerala middle class sitting room , furnished with dark red jack-fruit wood furniture. In front of me is a glass table with a tree trunk as its supporting legs. The sense of dullness that emanates from the paint of the furniture, proudly testifies to its age and the intricate woodwork found on the hand-rest , to the position the family held in its heyday. Through the window I can see the coconut trees dancing merrily to song sung by the slow breeze, free from any worries, enjoying the lazy Sunday afternoon reminding me that I am not in Bangalore. It was one of those moments that you wanted to capture forever. I enjoy this small concert nature has arranged for me for a while and then my eyes wander back to the contours of the room. The only thing that stands out from this tiny pi cute of sub-urban is the small picture of Veer Sarvakar alongside a bigger frame of a majestic old man, who as he later tells me, is KrishnEttan’s great-great grand father.

As I while away my time reading the latest edition of Jyothisratnam ( a astrological magazine in Malayalam), thinking about how I should spend all the money I am supposed to get according to the magazine, a skinny figure walks in to the room through the curtained door. As the curtain slides away revealing his features, the picture of Kerala gets duly completed . He’s wearing the traditional mundu along with a towel perched on his shoulders.

Before I get a chance to greet him, he starts profusely apologizing for making me wait. I find it hard to convince him that I enjoyed waiting in this perfect picture, as if from any novel by RK Narayanan. He nods at what I tell him but continues apologizing trying to explain the reason. He says that there was a sudden emergency in the locality since one of his neighbor’s sons had been caught smoking and the neighbor had brought the kid to him. He goes on to explain how improvised the kid’s family is and how, his mother has to work as a maid in 5-6 houses just to pay his college fees. His mom had brought him here so that KrishnEttan could put some sense into the guy’s head, Ettan being the only person the kid would listen to.

That’s KrishnEttan in a nutshell for you, greatly respected, greatly learned yet so humble in all his dealings that nothing can make you stop falling in love with him. Any respect you show to him is humbly returned back at you, which makes you feel important and intelligent, even though you know that no class can teach you what KrishnEttan has learned during his 70 odd years as a human being. Of course any question on his age returns a blank as he frankly confesses that he was not born onto a household which had the resources to record such information. But from his fond anecdote of having stayed up all night celebrating Indian freedom and then the subsequent freedom from schooling in the very next week due to the closure of village school gives you a rough idea.

As I sit there, he instructs his grand daughter to bring in some tea and jack fruit chips, proudly stating that it’s the jack-fruit tree that I passed in the veranda that bore the fruit we would be eating. We talk about many things, like the coconut disease, his cow that recently gave birth and the declining fertility of earth, things I would never get to talk about in Bangalore or even back in Cochin. Of course I am not at all good at such small talk, due to lack to knowledge if not a million other reasons, but KrishnEttan does most of the talking and puts you at ease, where you start thinking that you could go on talking about these subjects for hours and hours.

After a while we slowly move on to the purpose of my visit, to understand about the shop he runs at the town center. I (try to) explain it to him that I am trying to understand the impact of the retail boom that’s happening in India and which is going to hit Kerala soon. He seems a bit surprised when I project my concerns about the retail boom, especially its impact to the community shops like his. For the first time during this visit, we seem to be taking in two different languages. But soon KrishnEttan picks up; he starts asking me questions like how it is different from the Varkey’s or the 9-10 supermarkets that has been there for more than 2-3 years now. I explain to him the difference in scales of the ventures and how they can push the prices down and down. But after a while his ever infectious smile, which had been replaced by a thinner form of itself for a while, returns back with all its vigor.

As I finish I get the inkling that he has some story to tell me as I see his eyes widening up with memories of yesteryears. He keeps his glass cup, now half full with tea, down on the glass table and starts talking. “Our family is originally from Trivandrum and we moved here after selling all our ancestral property there in search of greener pastures. When my father set up shop here, his was one of the first shops at our now crowded town. At that time, this was not the “combuter-area” (IT Park) that it is now, and there was hardly anyone living near by. Most of his customers were daily wage laborers working in the near by factories. Wide-eyed youngsters and cynical veterans alike, coming from different parts of Kerala mostly out of necessity than choice. All the concrete building that you see today were plain fields and most of us lived in cottages weaved out of coconut tree leaves.”

He continues “With the savings my father had, we were one of the richest families in the neighborhood and initially set up his shop as a small tea shop for the laborers. My mom and sisters used to help my cooking the meals and later my and my siblings would go to school. We served good food at reasonable prices and soon enough we had all kinds of people coming and eating at our place right from the contractors to the laborers who worked for them. There were people to whom money was not a problem and there were also people who would get their wages only once in 3-4 months. My father always always gave credit to anyone who genuinly required it. Trust was the important commodity that he held in stock and that was what helped him build his business. He used to tell me “Don’t distrust a person until he gives you a reason to do so, and when he gives you a reason still never hesitate to give him a chance to atone”.People loved him and his store was like a second community center.

“As time passed, He saw that the people were struggling to get essentials like soap, powder etc from the city market which was 20 km away. In those times we didn’t have buses every 5 minutes like we have today and there was only a single KSRTC bus plying twice per day. So as a service to the people, he started to stock up on these items and sold them at a small margin.”

After the fire in my school, I also started working at the shop and as more and more customers demanded more and more things, we slowly increased our inventory. There was always a demand for all the things we stocked since the customers themselves were telling us what to stock. And with CEPZ and other factories coming, our customer base grew, as did our inventory. “

“When my father passed away, I took charge and with the “combuter-area” coming, sales only increased. The commodities that these newer people demanded fetched us better margin but that didn’t prevent me from stocking up on commodities our older customers required. And so even today our shop is used by both by the daily wage laborers as well as the combuter people and depending on the person I still offer credit if they need it. But coming to think of it, from the days of my father, its actually much easier for me to give credit since there are other assured revenue sources. Some of my customers have been shopping at my shop for more than 30 years and even the people started coming yesterday are always made to feel at home and whatever special requirement they have I try to personally see to it that they get it”

See Sabari, can the new supermarket offer this kind of service? Can they tell a boy that they knew his father and grand father? Can they know each and every customer by their name and be close enough to call them by their first name? Will they give credit to a person with no fixed income?

I stare at him with no words coming not just because the story has made me cry. As he narrated it, I could see the various images that flashed through his eyes, a part of me living through them, giving me a kind of vicarious pleasure/pain. I tell him he’s right and that supermarkets, however advanced and better, still cannot offer what his store offers. A part of me totally believes it as I say it, while the other part, knowing how the motive to make money drives even the noblest of acts in the corporate, trusts the ingenuous mind of the supermarket barons to come up with something to beat all this. But that’s for another day perhaps and a sense of contentment fills me, as a lot of my worries about the sustainability of his and similar business are dispelled .

He accompanies me as we step out, insisting on as least walking me back till the bus stop. As we make our way towards the bus stop thru a “kacha” path covered on one side by walls weaved from dry coconut leaves and open land with coconut and palm trees on the other, the heavens open up. As the tiny drops of water fall on the leaves, they remind me about evolution and the need to re-invent oneself. It’s as if the nature is talking to me in her language reassuring me that its not the end of the day for the hundreds of KrishnEttans of India

For A Heartfelt Love

For a Heart that once knew Love..
For those Lost times that made you Laugh..
For a Silence that Spoke more..
For those Eyes that showed Affection..
For every Breath that kept you Alive..
For the Passion that Pulled you through..
For those Broken Dreams and Desperate Desires
For every Heart that beats in Grief..
For a Tear that makes you Miss..

There lies an Empty Heart,
Which Once owned.. A Priceless Love..

This is the season that people are scrambling for Main projects for their B-Tech and I had written some posts about how to go about selecting your final year project (So you want to do a VLSI Project Part I, Part II and Part III) I have got tremendous response for those posts but, I have found that lots of people are finding it hard to make the transition from a computer programming language background to coding using HDL(when I say HDL I am talking about Verilog and VHDL since these are the HDL’s I know about, so some of my generalizations may not hold good for other HDL’s and thus any such mistakes are due to my ignorance and any comments are welcome. But the point is that this post is aimed at college level projects and for them HDL should have the same meaning as I do). So here are some tips to do that.

As you would find in most text books ( For Verilog I would recommend Samir Palnitkar’s Verilog HDL- A Guide To Digital Design and synthesis ), the different level of abstractions are behavioral, data-flow gate level and switch level. Enough has be written about them and I would recommend reading about them (LINK) Generally most code you write would be a combination of behavioral and data-flow styles of coding. What an abstraction provides is a different way to describe the hardware, which will be useful depending on the context.

It is very important to understand the philosophy/History behind HDL’s to use them. This is that there are two major motivations behind most HDL’s the two motivations are -:
1. To describe Hardware
2. To describe Hardware stimulus

This is a very simplistic view, but one I feel, that should be adopted initially. The basic problem with this is that, most people think only about the 1st motivation and assume that the synthesizer is some magic wand which will be able to construct hardware for any code we write. While this might be true in the future since we are moving more and more to algorithmic/behavioral level description of the hardware with higher level synthesis tools, with current Verilog and VHDL its not the case. Hence there is part of the language that is non-synthesizable What this means is that the some code that you write may not be automatically converted into equivalent hardware by the synthesizer. There are two reasons this

You are using the so called non synthesizable constructs in the language. To give a simple example, to model external stimulus or to model real behavior we can use “wait” command which is a delay command. But if we try to synthesize it, it will either give a error or a warning. It will give an error for a stimulus block since stimulus is a sequence of signals and their timing information and hence do not have any hardware equivalent and if we are using the wait to model delays within a module, the module will the synthesized and the delays ignored.

To understand this better lets see an example. Assume that you are writing a code that interfaces with an external EEPROM. Now once you write the code of your module you need to prove that it will work once we burn it on to a FPGA. To do this we move on to a phase known as “simulation” where the description we made of the hardware is used to model the behavior of our device. Now this will result in a Zero-Delay or Ideal simulation as all the constructs we use will happen instantaneously (but they will still be controlled by a generated clock and a sense of time will be there but the output of ,say, a inferred AND gate will be propagated instantaneously without accounting for the actual propagation delay in hardware) in the simulation where as when hardware works in FPGA, the delays will be present. Also since you need to interface to the EEPROM, you need to have a “Model” of the EEPROM to test your design against. This HDL model, which will be provided by the EEPROM vendor, will not contain the functional definition of the EEPROM but will be a behavioral model specified using actual observed delays (it can be best-case, worst-case or average delays depending on the model) so that it can be simulated. So here in this example, the module/block you write will be (should be) synthesizable where as the EEPROM will be a non-synthesisable model just for simulation. Also there will be a “test-bench” which will ensure that the correct connections between the modules are done and also any other external stimulus the two blocks requires are provided, for example your module might be controlled by a micro controller whose signals will be simulated by a micro-controller model within your test bench which will be a striped down model to give the control signals for your module. I hope this example makes the use of both styles of coding clear.

You are writing code that does not make sense from a hardware point of view. One common error is a doubly clocked flop or signals with multiple drivers.For example if you write code like

always @ (posedge clk or negedge clk)

it will throw an error while synthesizing. Why? From a C view this is fine since you are asking the always block to be activated at either of two events. But think of it from the hardware perspective
Consider the following code

always @ (posedge clk or negedge rst)
begin
if ( rst==0)
D<=1′=b0;
else
D <= Q ;
end

seeing this code a hardware engineer should see a simple D flip flop and not an if statement. Taking this analogy back to the earlier code you will see that you are asking the synthesizer to infer a doubly clocked flop which is not possible in hardware.

Another important problem that confronts a new HDL coder is called the “Synthesis-Simulation mismatch”. What this essentially means is that unless certain rules are maintained, the simulator will interpret and model what you write in a different way than what the actual generated hardware will behave like. This can lead to two cases, one in which the Simulation will work and actual hardware wont and vice versa. Both are dangerous since in the fist case your hardware wont work and in the second case you wont go to the hardware level as your simulation fails. This is generally due to small issues like leaving out signals from the sensitivity list etc. Instead of re inventing the wheel, I would suggest you read the paper [1] for a better understanding of this phenomenon

It is always encouraged that you have a very good understanding of how the simulator and synthesis process works to help eliminate errors. While should be the aim in the long run, adherence to some basic rules would help weed out most issues.

1. Always think about get an image of the hardware that you want to produce in your mind and then code it. Though it might seem really hard to do this the idea is not to think of all the hardware at once but to split the design into blocks of combinational logic followed by flops (Sequential design lends itself to this)

2. Always try to separate the combinational block and sequential blocks into different always/process blocks. This helps in debugging errors later and also simplifies coding

3. When modeling sequential logic, use non-blocking assignments. For reasons for 3-10 see [2]

4. When modeling latches, use non-blocking assignments.

5. When modeling combinational logic with an always block, use blocking assignments

6. When modeling both sequential and combinational logic within the same always block, use non-blocking assignments.

7. Do not mix blocking and non-blocking assignments in the same always block.

8. Do not make assignments to the same variable from more than one always block.

9. Use $strobe to display values that have been assigned using non-blocking assignments

10. Do not make assignments using #0 delays.

11. If you are having to use #1 delays read this Verilog Non-blocking Assignments With Delays, Myths & Mysteries

12. Use asynchronous resets wherever possible ( Being a DFT engineer I should not say this as it complicates DFT ;)). Read [3] To understand more.

13. If you are using state machines in your design read State Machine Coding Styles for Synthesis.

14. Try to avoid Dangling wires Due to misspelling (very common!) or unused signals, there might be dangling wires in the design. The synthesis tool might optimize these wires away.

15. Specify all conditions explicitly for ‘case’ Statement or “if else” Statements - To avoid problems with inferred latches

16. Understand the differences between ‘case’ vs. ‘if – else’ Statements - In general, case statements would translate to parallel muxes in hardware. Meanwhile, the use of if – else statements results in priority-based hardware, which can slow down the overall implementation of the design. Thus, only use if – else statement when priority-based hardware is required. Otherwise, use case statements to avoid possible inefficient implementation of the design.

17. When using an always statement to implement combinational logic, the sensitivity list has to include all signals that appear on the right hand side of the assignments inside the. This is to avoid synthesis simulation mismatches.

     

Finally but a very important time saver can be to try and get hold of a good Linting tool so that a lot of these errors and others are caught before going to the FPGA stage.

I hope that this was helpful and more comments/tips/questions are welcome.

References
[1] RTL Coding Styles That Yield Simulation and Synthesis Mismatches (SunBust Design)
[2] Non-blocking Assignments in Verilog Synthesis, Coding Styles That Kill!(SunBurst Design)
[3] Synchronous Resets? Asynchronous Resets?I am so confused!How will I ever know which to use?(SunBurst Design)

Finally some good news this week…Blue boys come to india
Ok to call Hibbert a EPL star is overkill but still he’s “something”