a mARTIAN dIARY

Continuing from part I

Project Considerations

Like I mentioned earlier a VLSI project is different for the different considerations that you must put in first as opposed to another “ordinary” project. If you do a FPGA based project, you are eliminating some of the issues existing with other type of VLSI projects like aligning with the foundry timing but still there are other important points. Here are some of the considerations that I feel must be well thought off before venturing into a VLSI project.

Facilities, Faculty and Tools

VLSI is a relatively new domain and hence this is one consideration that must go in earlier that other. Ask some questions to yourself

Who would be responsible for providing me with the FPGA Hardware?
In case its to be done your self, it can be a costly affair as a FPGA kit can cost over 30-40k Rs factor that in
In case it’s the college authorities, make sure that the FPGA kit is already available and also that’s its working properly. Most importantly check that someone knows know to use it at least in a rudimental fashion because otherwise you could end up spending a substantial time learning how to use the FPGA rather than doing the “actual” project. It is true that you would have to allocate sometime for learning the FPGA and to program it but it should only take up a reasonable amount of your total project time.

Who would be responsible for the software?
Like I said there would be two parts to the project. One is to be done at the software level (Major Part) and other at the hardware level. The software for the same can be very costly if you go for full fledged versions. In any case select the software to be used pretty early in the cycle and also try to go for software which has been used by someone you know so that there would be a quick resolution point for issues. Also Take at look at some of the free software that I have mentioned later.

Why not an External Agency?
In case you taking the help of a external agency ,  a training center or project center or going in for internship somewhere [Places I know that offer VLSI internships include ISRO, CEERI Pilani, IIT’s and IISc etc but you need to initiate the process very early ].  (for want of facilities or tools or faculty) Please make sure that you understand first itself what your level of involvement  in the whole project would be. It might do you good to have a completely working project done and delivered by them as far as marks as concerned by it wont do you any good once you come to the industry and you are expected to know certain stuff on account of you having done such a project already

Topic Selection

Another important thing to consider is the topic or the core of the project. Here people tend to be a bit extravagant with their choices. Understand that you are going into a new domain, learn a new language, learn new tools and then finally implement them. In case some part of this is already done, well you can go ahead and take “harder” projects but try not to bite too much than you can chew.

Personally I would recommend a “phased” approach. In this approach you take up a base issue say I2C. Then you look at the minimal features that need to be implemented, for example 7 bit addressing and just master mode or slave mode operation. This is what you should commit to the college also. Then if you are successful in doing this within your time frame you can go ahead and implement the advanced features. I will list some topics for consideration and my opinion on them later. (See part III)

Some Free tools and Links – :  (http://www.cs.iitm.ernet.in/~noorse/new/resources.html)

IRSIM Switch level Simulator
IRSIM is a tool for simulating digital circuits. It is a "switch-level" simulator; that is, it treats transistors as ideal switches. Extracted capacitance and lumped resistance values are used to make the switch a little bit more realistic than the ideal, using the RC time constants to predict the relative timing of events.

Netgen (Layout vs. Schematic)
Netgen is a tool for comparing netlists, a process known as LVS, which stands for "Layout vs. Schematic". This is an important step in the integrated circuit design flow, ensuring that the geometry that has been laid out matches the expected circuit. Very small circuits can bypass this step by confirming circuit operation through extraction and simulation. Very large digital circuits are usually generated by tools from high-level descriptions, using compilers that ensure the correct layout geometry. The greatest need for LVS is in large analog or mixed-signal circuits that cannot be simulated in reasonable time. Even for small circuits, LVS can be done much faster than simulation, and provides feedback that makes it easier to find an error than does a simulation.

Digital Standard Cells
This is an excellent source for LEF and GDS standard cells. The cells are all compatible with the MOSIS SCMOS rules for the various processes available through MOSIS (mostly TSMC and AMI, 0.18um to 0.5um).

VIS (Verification Interacting with Synthesis)
Verilog compiler (vl2mv) and logic verification. VIS (Verification Interacting with Synthesis) is a system for formal verification, synthesis, and simulation of finite state systems.

Logic optimization using SIS
This tool takes the BLIF format description and creates a reasonably good netlist representation using a set of standard cells described in the "genlib" format. SIS will do synthesis of both synchronous and asynchronous sequential circuits.

Verilog Compiler (Iverilog)
Icarus Verilog is a Verilog simulation and synthesis tool. Iverilog. (Latest)

Verilog Compiler (Iverilog) for Windows
Icarus Verilog is a Verilog simulation and synthesis tool

GTKWave (Electronic waveform viewer)
GTKWave is a digital waveform viewer useful for examining the output of various digital simulators (like Icarus Verilog, for example). It can read VCD, EVCD, LXT, and Synopsis output formats. It was built using the GTK+ toolkit.

Language Selection/Learning

This is another important decision to be made. Some of the important languages that you can use are Verilog, VHDL, SystemC, System Verilog etc.

For a normal engineering student with background in C there is a important distinction to be understood between coding in C and other software languages and HDL’s.  At one level most people emphasize that there is no concept of time in C and a different connect of parallelism. As far I see it even thought this is a correct way of stating the difference there is to be understood in a different way. This is something very important which will explain in another post.

As far as section is concerned SystemC and System Verilog have a lot of features which make it beneficial for verification so if you plan to place a lot of emphasis on verification and simulating (which you ideally should be but may not work within given timeframe). And of the two I think System Verilog is the language of the future.

As far as VHDL and verilog is concerned. Both are fine, but I have a bias towards verilog (even though I did my academic project in VHDL) mainly because I feel it is easier to learn that VHDL. VHDL in a sense is very structured which has a lot of uses when it’s a huge project, but in the structure it’s easier for a newbie to get lost.

Another Important point which is not stressed at the college level (at least mine) was the power that a scripting language can provide. If your working on Unix Shell it self would be enough and TCL is a good choice in Windows environment (and Unix too). If some of the tasks can be automated, a lot of time can be saved and also final presentations can be given that “professional” touch. But you have to objectively plan whether usage of a new language would save time or waste it ???

Project Planning

As is often said (but not done enough) Prior Planning Prevents Poor Performance. Planning is a very important phase of any project let alone one such as this. Also try to factor in as many risks as possible. End of the day remember that even seasoned managers get planning wrong but still the project goes ok. Just remember that it’s a facilitator than the deliverable. Some of the phases that must be considered include

1. Ramp-Up VLSI Basics/Coding – Must be done as soon as possible and should reach a reasonable level of comfort here by writing smaller projects
2. Ramp-Up Hardware – Must be done as soon as you get your hands on the hardware. Try to implement smaller things like counter etc and see the LED’s blinking
3. Design Phase – Try to visualize the whole project to be split into parts that can be independently coded and tested. Not all parts may be possible but as a general rule try to visualize the hardware before writing it. A study of designing writing good state machines (if required) is good. 
4. Coding Phase – This is some of the phases that can be sped up. Try to the capabilities of the tool to maximum. For example some tools might write out and give simple structures like FIFO etc. Unless the project is too simple and there are just FIFO’s and simpler stuff try to use the tool for the same. Make sure you understand all the code the tool generates except for maybe some macros etc.
5. Verification – All individual modules should be verified by subjecting it to simple test-cases. Ideally as soon as you start coding you project, someone else (other than the coder) should start on a test bench to test the code that is being written. Ideally both should not communicate with each other how they are implementing their work and should take all information from the specifications document detailing the specification. The idea is that if the person developing the testing environment and test cases come s to know of the intricacies design, he might get subconsciously biased and a true verification might not take place. How much of this is actually possible is something should be decided based on different constants that are on a academic project.
6. Some level of automation using scripting languages, if pre-planned can save a lot of time

Documentation

I know from a personal perspective that documentation can be a pain in the wrong place. But if you have a rough document where you pen down your experiences, it can be very helpful while making a final formal document. It has other uses like being helpful for other team members and also for your juniors.

Some Other Ideas

Also if you are really interested some other ideas include

1. Study Group – In case more than one team is doing different VLSI projects, a study group within the college would be very beneficial for all the teams. It might help not to  re-invent the wheel , so to speak , if there is proper communication between the teams both at the learning phase and also at the implementation phase
2. Another thing that can make things interesting is to start up a blog to document your experiences. This is true for any kind of project though. It is generally very common outside India I believe. It can help other doing similar work to discover you and ask for help or help you out. We had done something simlar, but our laziness got the better of us FreeCan

I hope this is helpful in your endeavor and do let me know of your experiences- successes and un-successes (there are not nothing as failure as long as you learn a few new thing….which I am sure you will) and don’t hesitate to contact me for any help you think I can provide

Continue reading Part III