a mARTIAN dIARY

So I am about to finish my first year as an EDA engineer. It does put me a scale up in terms of being an engineer with 1 year industry experience. Hurray(?)!!!.

Now how can I call it a COMPLETE year without attending one the Major calendar events in every EDA-using engineer’s year? Yep….this feeling was so strong that I finally registered for SNUG and Cadence Technology on tour and ended up attending them as well.  Here is what I thought of both

SNUG 2007

For the uninitiated,  SNUG stands for SyNopsys User Group and it is a yearly conference for users of synopsys tools (Synopsys being a major EDA tool vendor with Cadence Mentor Graphics and Magma being the other biggies). In hindsight, the turn-out was really good. Also, for me, working primarily on the synopsys tools, the organization of the tracks made sense. Tracks are basically parallel programs sessions specific to domain of the engineer. For synopsys its organized as “Physical Design & SignOff”, “Synthesis and Test”  and least but miles ahead of least (No I am not a verification engineer ) the “Verification and AMS” track. Since a lot of work in India takes palace in the verification field (so I am lead to believe), this track generally attracts the biggest crowds with “Synthesis and Test”  having the lowest participation.

We were asked to reach the place at around 7:15 ( Were they bonkers I wonder?) at Leela Palace and for a morning hater like me this was a pressure-point….but I managed to reach there by 8:30, pretty good considering it was still MORNING The registration was pretty hassle free as the kit and ID cards were already prepared for the pre-registered people and were set up in alphabetic order. We just needed to show our ID card to get the same. I knew that these EDA vendors are pretty generous with gifts but was really surprised to find a USB Mouse!!! and a Laptop Light!!! along with the kit. Not a total waste already eh? Funny how sometimes even the most useless things excite you the most when they are free, as in my case being a non-laptop owner, both the gifts meant nothing in terms of actual practicality. Anyways I followed the flow and stood in the line for breakfast. Not that I am much of breakfast eater but again free is the keyword :P. One thing I found to my liking was that, it was a hotel run by “coconut-oil-eating-south-Indians” to which category I belong and found that the food resonated with my taste-buds.

Anyways after the breakfast and exchanging pleasantries with my senior Niyas from TI, I found a seat to hear the keynote address from Derdre Handford Sr. VP of Global Technical Services, Synopsys and customer keynote from Behrooz Abdi Sr VP and General Manager CDMA Technologies, Qualcomm Inc. Most of the keynote was focused on Low power, a trend I later observed at Cadence TOT too. Personally, It was really nice to see a Iranian at the head of Qualcomm though I am not much experienced to know/not know that’s its common/uncommon.

Anyways, after the intro the people split into their different tracks. This is one thing I found odd. Since the attendance of the even was huge! The people were not fitting into a single hall anyway and all of them were accommodated by using different halls with video stream from the main hall. But still they did not divide the people based on track initially itself and so after common sessions, people needed to move between the rooms. I feel they could have divided the people initially it self based on track to their respective rooms to avoid such confusion.

Anyways coming to the “technical” details, the sessions were divided into panel discussions, synopsys tutorials, user papers and poster paper. Panel discussions were mainly focused on the theme of “low-power” so to speak. The rest were specific to the track and I can speak for the Synthesis and test track.  Most of the tutorials were focused on the Design Compiler – Topographical technology, which according to Synopsys is the next-big-thing in synthesis and there were a lot of user papers parroting the same.
“A paper titled Dynamic Shift Frequency Scaling Of ATPG patterns” from Open Silicon was a very good paper and it rightly won the best paper award. I think you can get more details at the SNUG India site

One of the strangest things was that on the first day, there was no chicken dish in the lunch (typically Indian eh?). Fish and mutton?? :P. Diner was looking good but I had to escape to my friend’s birthday bash.

So what were the takeaways?

• Got a overview of the DFT practice in India/Banglore , at least of companies that use Synopsys flow
• Companies include TI, Intel, Open Silicon, MindTree, Wipro etc
• Got an exposure to DFT-Topographical.
• Got an idea of focus areas for me to develop as a DFT Engineer.

On a side note I went to and Cadence Technology on tour the next week at Taj Residency Banglore. They were at least more sensible and gave out better timings as 8:30 reporting time and since the participation was lesser it seemed better organized. But since the only tool I use of cadence is LEC, wasn’t of much interest/ relevance to me. Their new SDC checker feature seems good as a lot of false paths can be identified and SDC redundancy can be removed. But it seemed like a logical extension of the technology rather than an innovative jump. Their free gift is currently gracing (or is it the other way around) my house in Kochi

BUT they were sensible and had chicken as a side course just in case you’re wondering