I thought I would write description of the various jobs in the VLSI industry for the concerned fresher (that’s me 1 year on the rewind). I would have loved something like this last year. Hopefully this is helpful to at least someone. Let me know if anyone wants any more details.
ps: I have tried not to re-invent the wheel at places if you know what I mean 
Architecture Designer: This the top-most level where team defines the
design of the chip according to the specifications. Usually this is a job that is done by people with extensive knowledge of the field i.e. with a LOT of experience or people with PhD’s and M-Tech’s.
Logic Designer: Team at this level implements the defined design. These people design the functions or modules of the chip to perform the well-defined tasks described by architecture team. This design is written in an HDL language such as Verilog or VHDL. On synthesizing the design a "netlist" is generated. The netlist is actually a gate level representation of the hardware description that is written at higher level in the HDL. VHDL vs Verilog is a question that most people ask. I feel its better to know both since; a project might require knowledge of both. In the industry a large amount of projects are done in Verilog.
Verification engineer: These people write test-benches (simulation environments and stimuli) and test that the logic designed is performing according to specifications. For this they can use verilog and VHDL itself for small modules or can use verification specific languages like e-language or SystemVerilog. In the test environments they created models of devices that the design would be interacting with in real life and try to simulate real usage scenarios for the design. They also run their test cases on the netlists generated
After this stage the roles are largely dependent on whether you are working on a ASIC based project or a FPGA based project. I shall first talk about ASIC flow.
Synthesis & DFT Engineer: This is the work that I currently do. We take the RTL code that’s written by the logic designer and synthesize it to get a netlist. We give various constraints on timing, area etc to make sure that the overall system goals are reached. We also use some formal verification methods to make sure that mathematically the RTL which was delivered to us and netlist that we generate are equivalent. After that we analyze the logic and insert extra logic to facilitate testing at a later stage. This is called DFT(Design for testability). We also check what percentage of possible problems can be detected and if its not satisfactory, the design is sent back for a re-spin. Once the fault coverage goals are met, the netlist is handed over to physical designer, along with timing information generated during synthesis level. At this point the timing is not exact and is just a estimation based on various technologies.
Physical Designer: This team make "layout" for the design using "netlist". Layout is used to produce masks for fabrication of the chip. The are the people who are responsible for timing closure. Since they have the closest estimate of timing at the simulation level, they need to make sure that timing is met properly. If they are unable to do so they will send the design back though the flow.
Library Designer: They design the logic gate library that physical designer use. They create logic gates on different process (90nm,65nm etc), of different speed/area combinations.
After this Physical designer’s work the layout is sent to the fab and chips are manufactured. The rest of the flow is referred to as post-si(licon) tasks.
Coming back to the FPGA flow.
Synthesis/ Implementation Engineer: Is responsible for mapping the logic generated from the RTL to FPGA using FPGA tools. After that they also make sure that some of the test cases pass so that they can say that the design is working in the FPGA
Testing Engineer: runs tests on the chip (FPGA and ASIC) to ensure proper functionality of the chip. They make use of data provided by the DFT engineers to run tests to detect any faults. They also do characterization of devices like memories and other devices.
Board Designers: Till now we were concerned with activities happening at the chip level. Once the chip is manufactured (actually the flows begins much earlier with just the foot print of the chip), boards are designed which would be utilizing the chips in various applications. The company developing the chip would be designing reference boards, which would showcase the capabilities of the chip and customer companies would be using the chip in their board for their product. They work with CB design tools like allegro and orcad
Signal Integrity Analysis: It does not come under board testing in general…whats done in testing is actually waveform scoping (on oscilloscope or on logic analyzer) , changing the bin files of fpga (fpga designer) and observing its effects. Also general functionality checking with the help of JTAG.
SI has got 3 parts- prelayout simulation, post layout simulation and onboard testing
In prelayout using the input-output buffer models, we develop the topology and simulate it to see its effects…we will be adopting appropriate terminations, trace length etc to get the expected results (like reduced crosstalk, jitter etc).in post layout we generate topologies from board files (CAD results) and simulate to see whether it matches with prelayout results. If not matching, suggest the required changes…and on board testing is the final real board testing, expecting everything to work fine…no more modifications possible her
(Thanks to Niviya Chacko from Wipro VLSI for this input)
Board Testing: They test that the board is working properly. (Will update later)
