Hold time violations in Shift registers?
Interesting question…eh?
See for a sequential circuit we want the t (hold) < t (contamination) + t (wire delay)
Now t (wire delay) is something I used to always neglect(yes yes my fault :P) , so the constraint is
t (hold) < t (contamination)
but for a shift register there is not combo-logic between the two registers, hence t (contamination) is 0
then How is the hold time constraint met?
…its probably due to the t (wire delay) but isn’t it fascinating we never thought of this….
