Interesting question…eh?
See for a sequential circuit we want the t (hold) < t (contamination) + t (wire delay)
Now t (wire delay) is something I used to always neglect(yes yes my fault :P) , so the constraint is
t (hold) < t (contamination)
but for a shift register there is not combo-logic between the two registers, hence t (contamination) is 0
then How is the hold time constraint met?
…its probably due to the t (wire delay) but isn’t it fascinating we never thought of this….
I dont want to sound brash but I feel at least 70% of the base knowledge by a EDA engineer is in the following lines.The rest of the knowledge would come from this base and depend on the domain I feel
Setup time (Ts)
is the time interval immediately preceding the positive transition of the clock input, during which the system must maintain the data at the input to ensure its recognition.
Hold time (Th)
is the time interval immediately following the positive transition of the clock input, during which the system must maintain the data at the input to ensure its continued recognition.
Combinational-logic delay (Tcomb)
is defined as the time required for signals to traverse the combinational logic.
Propagation delay (Tp)
is the time taken for changes in the clock input to affect the outputs.
