Virtual Clocks
(From a yahho goup I subscribe to)
By definiton, virtual clock is a clock which doesn’t have any design object associated with it.
Virtual Clocks are generally used to constraint the IOs (Inputs & Outputs) of a block.
Consider a big design with two sub-blocks, block ‘A’ and block ‘B’. Suppose there is a timing path going from a register x_reg (clocked by ‘clk1′) (in block A) to register y_reg (clocked by ‘clk2′) (in block B).
If you are analyzing this design at the top-level, the analysis tool can associate both the clocks with some design objects and hence there is no need for virtual clocks.
Now if you are doing analysis at block-level (say Block ‘B’), and you have to tell the tool that timing path ending at y_reg register is launched by a clock "clk1". The only way to do this is to create a virtual clock.
For creating clk2 you have some design object (port/pin) available, since it exist in block ‘B’ itself. But block ‘A’ is out of the scope of the current environment, and you have to define "clk1" as virtual clock.
