Public shows of affection…
Recently I went home after 4 months of working in UK, and to cut a long and sentimental story short, it was wonderful. It was wonderful to see the tear laid eyes of my mom, shortly revisit the hardened cynicism of my father and last from far from least the sweet tender sight of love. HOME SWEET HOME!
Anyway while coming back, I was at the station just about to board the train. The train was already late….something common to the “special” trains. Then I remembered something I promised myself when I was in UK….to hug my father and mother and me being me, I gave into my impulse and hugged my mom. My dad in had his usual nonchalant mask on, but I am sure was pretty sad that I was leaving so soon, anyways as I starting hugging him, commented “public shows of affections are shams”….at that time I was too involved in following my impulse that I did not heed to it. But it stuck to me like chewing gum.
Later while my mind was wandering through the universe, hoping from one planet to another, with nothing else to do during the train journey, this comment revisited me with renewed vigor. At the surface of it, it seems plausible, as its safe to assume that a lot of people do show affection in public just to one-up on someone watching. I would not consider myself as completely out of that group of people, since I have used these kinds of mind-games (?) more than once. For instance when I was having fights with some of my friends, I used to get extra cuddly with other friends around him/her. Similarly when I have heard stupid rumors floating about cracks in my relationships, I have put on that extra effort of showing my friendship…not to my friend but to others who were watching, like putting on that extra make-up on your comeback film.
In UK it was not hard to find love-stuck couples locked in their lips and more even in the sleepy town of Southampton….where they more worried about others or just enjoying the moment? And what about our own “desi” couples in banglore?
But all these things aside, the action that led to this particular comment had none of these factors as its parents. It was just an impulsive act on part of a son who really missed his dad. Maybe what he said is true and most public acts of affection are just sham…but as long as its not the crowd that you care about and u get that “good” feeling in your heart I feel its ok….and maybe…this over analysis has to STOP! :p
Interesting question…eh?
See for a sequential circuit we want the t (hold) < t (contamination) + t (wire delay)
Now t (wire delay) is something I used to always neglect(yes yes my fault 
) , so the constraint is
t (hold) < t (contamination)
but for a shift register there is not combo-logic between the two registers, hence t (contamination) is 0
then How is the hold time constraint met?
…its probably due to the t (wire delay) but isn’t it fascinating we never thought of this….
I dont want to sound brash but I feel at least 70% of the base knowledge by a EDA engineer is in the following lines.The rest of the knowledge would come from this base and depend on the domain I feel
Setup time (Ts)
is the time interval immediately preceding the positive transition of the clock input, during which the system must maintain the data at the input to ensure its recognition.
Hold time (Th)
is the time interval immediately following the positive transition of the clock input, during which the system must maintain the data at the input to ensure its continued recognition.
Combinational-logic delay (Tcomb)
is defined as the time required for signals to traverse the combinational logic.
Propagation delay (Tp)
is the time taken for changes in the clock input to affect the outputs.
- Moore’s Law : The number of transistors on a chip doubles annually
- Rock’s Law : The cost of semiconductor tools doubles every four years
- Machrone’s Law: The PC you want to buy will always be $5000
- Metcalfe’s Law : A network’s value grows proportionately to the number of its users squared
- Wirth’s Law : Software is slowing faster than hardware is accelerating
Except for Machrone’s law I feel everything stikes a chord within me….but I guess if you always go for the latest most bestest and garandanglus (if thats a word) that would also hold true….not for cheapos like me who go for second hand computer models
From “5 Commandments”, IEEE Spectrum December 2003, pp. 31-35
(From a yahho goup I subscribe to)
By definiton, virtual clock is a clock which doesn’t have any design object associated with it.
Virtual Clocks are generally used to constraint the IOs (Inputs & Outputs) of a block.
Consider a big design with two sub-blocks, block ‘A’ and block ‘B’. Suppose there is a timing path going from a register x_reg (clocked by ‘clk1′) (in block A) to register y_reg (clocked by ‘clk2′) (in block B).
If you are analyzing this design at the top-level, the analysis tool can associate both the clocks with some design objects and hence there is no need for virtual clocks.
Now if you are doing analysis at block-level (say Block ‘B’), and you have to tell the tool that timing path ending at y_reg register is launched by a clock "clk1". The only way to do this is to create a virtual clock.
For creating clk2 you have some design object (port/pin) available, since it exist in block ‘B’ itself. But block ‘A’ is out of the scope of the current environment, and you have to define "clk1" as virtual clock.
