a mARTIAN dIARY

In reference to chip testing

Yield loss is that fraction of good chips from  the total number of chips that are rejected as bad chips during testing

Defect Level is that fraction of bad chips that are passed during testing as good chips

This issue occurs because to create ideals tests or defect based tests  is very hard due to the complexity in modeling the real defects properly and also the inability to exhaustivily cover all real defects. Instead "fault models" like stuck at fault etc are develops which does not map on to real defects 100%

Hence some good chips are rejected and some bad chips are passed

Good chips   Prob of pass = high       Mostly good chips
                ———————>>
                *                 *
   Prob Of Fail *           * Prob of pass
        (Low)       *     *    (Low)
                         *
                       *   *
                     *        *     
                  *              *
                *                   *
 Bad Chips   —————–>>  Mostly Bad Chips
                      Prob Of Fail
                         High