False Paths
False paths are that do not propagate signals events. It usually because the convergence of fan-out to surrounding logic such as the select line in the picture. Since there will be no signal propagation through a false path, it need not be considered while doing timing analysis or optimization.
Some example includes -:
• As in the example shown above, the longest path (6ns) is never excited and the critical path (4ns) of this combination logic gives is less than that.
• Another case maybe when, even if a signal propagation is possible, it might never be excited by the logic , say a logic excited by a don’t care state in a state machine.
• Paths between any two asynchronous clocks.
Multicycle paths are paths which take more than a single cycle. The Tools by default , takes all the paths to be single cycle operation . So they need to be ignored too.
The above are due to structural. Another case is when a path is contributed by a test mode. Since we might be running test modes at lower speeds and they are never excited in normal mode, they can be ignored during timing analysis
Reference
Logic Synthesis and Verification by Soha Hassoun, Tsutomu Sasao
